1. A leakage control circuit for a complementary metal-oxide semiconductor (CMOS) gate, comprising:
a CMOS logic gate comprising a first N-type metal-oxide semiconductor (NMOS) transistor and a first P-type metal-oxide semiconductor (PMOS) transistor, each transistor having a body terminal, a drain terminal, a source terminal, and a gate terminal; and
a control circuit coupled to said CMOS logic gate via any of said first NMOS transistor and said PMOS transistor, said control circuit comprising:
a first transistor coupled to the body terminal of any of said first NMOS transistor and said PMOS transistor to bring said body terminal to a first reference potential; and
a second transistor coupled to said body terminal of any of said first NMOS transistor and said PMOS transistor to bring said body terminal to a second reference potential, said second reference potential provided by a body bias voltage supply that provides a bias voltage to establish a predetermined current enhancement ratio (CER).
2. The circuit of claim 1, wherein said CER expresses a ratio between a current of said drain of any of said first NMOS transistor and said PMOS transistor with body bias to a current of said drain of any of said first NMOS transistor and said PMOS transistor without body bias.
3. The circuit of claim 1, wherein said CER expresses a ratio of width over length of a reference current device and a width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.
4. The circuit of claim 1, wherein the CMOS gate any of an inverter, NAND, NOR, AND, OR, XOR, NXOR, AND-OR, and OR-AND.
5. The circuit of claim 1, further comprising:
a second CMOS logic gate, wherein said leakage control circuit controls leakage of said second CMOS logic gate.
6. The circuit of claim 1, further comprising:
a voltage shifter coupled between a drain terminal of said second transistor and said body bias voltage supply.
7. The circuit of claim 1, further comprising:
a voltage shifter coupled between a source terminal of said second transistor and a drain terminal of said first transistor.
8. The circuit of claim 1, further comprising:
a capacitor coupled between a gate terminal of said second transistor and a source terminal of said second transistor.
9. A circuit, comprising:
a first MOS transistor having a gate terminal, a source terminal, a drain terminal, and a body terminal; and
a control circuit coupled to said MOS transistor, said control circuit comprising:
a second MOS transistor coupled to said body terminal of said first MOS transistor to bring said body terminal to a first reference potential; and
a third MOS transistor coupled to said body terminal of said first MOS transistor to bring said body terminal of said first MOS transistor to a second reference potential, said second reference potential provided by a body bias voltage supply to establish a predetermined current enhancement ratio (CER);
said control circuit controlling leakage of said first MOS device.
10. The circuit of claim 9, wherein said CER expresses a ratio between a current of said drain of said first MOS transistor with body bias to a current of said drain of said first MOS transistor without body bias.
11. The circuit of claim 9, wherein said first MOS transistor is any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.
12. The circuit of claim 9, wherein said CER expresses a ratio of width over length of a reference current transistor and a width over length of an adaptive body bias transistor, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of said current mirror circuit of said body bias voltage supply.
13. The circuit of claim 9, wherein said MOS device comprises a portion of a logic gate.
14. The circuit of claim 13, wherein said logic gate comprises any of an inverter, NAND, NOR, AND, OR, XOR, NXOR, AND-OR, and OR-AND.
15. The circuit of claim 9, wherein said control circuit is connected to at least one other MOS transistor of the same type as said MOS transistor.
16. The circuit of claim 9, further comprising:
a voltage shifter coupled between a drain terminal of said third transistor and said body bias voltage supply.
17. The circuit of claim 9, further comprising:
a voltage shifter coupled between a source terminal of said third transistor and a drain terminal of said second transistor.
18. The circuit of claim 9, further comprising:
a capacitor coupled between a gate terminal of said third transistor and a source terminal of said third transistor.
19. A body voltage control circuit for controlling leakage of a metal-oxide semiconductor (MOS) transistor, comprising:
a first transistor coupled to a body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a first reference potential;
a second transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a second reference potential; and
a body bias voltage supply coupled to said second transistor to establish a predetermined current enhancement ratio (CER).
20. The circuit of claim 19, wherein said CER expresses a ratio between a current of said drain of the MOS transistor with body bias to a current of said drain of the MOS transistor without body bias.
21. The circuit of claim 19, wherein the MOS transistor comprises any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.
22. The circuit of claim 19, wherein said CER expresses a ratio of width over length of a reference current device and a width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.
23. The circuit of claim 19, further coupled to a second MOS transistor to control leakage of said second MOS transistor.
24. The circuit of claim 19, further comprising:
a voltage shifter coupled between a drain terminal of said second transistor and said body bias voltage supply.
25. The circuit of claim 19, further comprising:
a voltage shifter coupled between a source terminal of said second transistor and a drain terminal of said first transistor.
26. The circuit of claim 19, further comprising:
a capacitor coupled between a gate terminal of said second transistor and a source terminal of said second transistor.
27. A method of manufacturing a leakage control circuit to control leakage of a metal-oxide semiconductor (MOS) transistor, comprising the steps of:
forming the MOS transistor on a substrate, the MOS transistor having a gate terminal, a drain terminal, a source terminal, and a body terminal;
forming a first MOS transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a first reference potential; and
forming a second MOS transistor coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a second reference potential;
said second reference potential provided by a body bias voltage supply that provides a bias voltage to establish a predetermined current enhancement ratio (CER).
28. The method of claim 27, further comprising the step of:
expressing said current enhancement ratio (CER) as a ratio between a current of said drain of the MOS transistor with body bias to a current of said drain of the MOS transistor without body bias.
29. The method of claim 27, further comprising the step of:
expressing said CER as a ratio of width over length of a reference current device and a width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.
30. The method of claim 27, said MOS device comprising any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.
31. The method of claim 27, further comprising the step of:
forming a connection between the leakage control circuit of claim 27 and a second MOS transistor to control leakage of said second MOS transistor.
32. The method of claim 27, further comprising the step of:
forming a voltage shifter coupled between a drain terminal of said second transistor and said body bias voltage supply.
33. The method of claim 27, further comprising the step of:
forming a voltage shifter coupled between a source terminal of said second transistor and a drain terminal of said first transistor.
34. The method of claim 27, further comprising the step of:
forming a capacitor coupled between a gate terminal of said second transistor and a source terminal of said second transistor.
35. A method for controlling leakage current of a MOS transistor comprising a gate terminal, a drain terminal, a source terminal and a body terminal, the method comprising the steps of:
supplying a first reference voltage to the body of the MOS transistor with a control circuit to bring the body terminal of the MOS transistor to a first reference potential;
supplying a second reference potential to the body of the MOS transistor with said control circuit to bring the body terminal of the MOS transistor to a second reference potential; and
supplying a bias to said control circuit, wherein said second reference potential establishes a predetermined current enhancement ratio (CER).
36. The method of claim 35, wherein said CER expresses a ratio between a current of said drain of the MOS transistor with body bias to a current of said drain of the MOS transistor without body bias.
37. The method of claim 35, wherein the MOS transistor comprises any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.
38. The method of claim 35, wherein said CER expresses a ratio of width over length of a reference current device and width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of a body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply, said body bias voltage supply provided to said control circuit.
39. The method of claim 35, further comprising the step of:
supplying said first reference voltage and said second reference voltage to a second MOS transistor to control leakage of said second MOS transistor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Device for explosive drilling by means of explosive capsules with a firing device for firing the explosive capsules at a material to be stripped,
wherein
at least one container with liquid oxygen and at least one container with at least one fuel component are provided,
in that a combining device is arranged for combining the fuel component with the liquid oxygen for the forming of the explosive capsules and
in that a supply device is provided for supplying the formed explosive capsules to the firing device.
2. Device according to claim 1,
wherein
in the combining device the fuel component can be formed into shaped bodies, in which case the fuel component can be mixed with the liquid oxygen beforehand or afterwards.
3. Device according to claim 1,
wherein
enveloping bodies, prefabricated capsules containing fuel andor ignition elements can be supplied to the combining device in order to form the explosive capsule.
4. Device according to claim 1,
wherein
a tube-shaped drilling body is provided, in the lower end portion of which at least one aperture of the firing device is arranged.
5. Device according to claim 4,
wherein
in the portion of the aperture a gas nozzle arrangement is designed.
6. Device according to claim 4,
wherein
in the lower end portion of the drilling body a stripping member, in particular cutting teeth andor roller bits, is arranged.
7. Device according to claim 1,
wherein
a discharging conveyor device, in particular an auger, is arranged for conveying away the material to be shattered.
8. Device according to claim 1,
wherein
the firing device has a pneumatic or hydraulic feeding device.
9. Device according to claim 1,
wherein
an adjusting device is provided, with which a selected part of the working face can be fired at for directional control or control of the drilling progress.
10. Method for explosive drilling,
wherein
an explosive with liquid oxygen is used.
11. Method according to claim 10,
wherein
explosive capsules are formed of at least one fuel and the liquid oxygen immediately before being supplied to a firing device and the explosive capsules are fired by the firing device at a material to be stripped in order to explode thereon and shatter the material.
12. Method according to claim 10,
wherein
the explosive capsules are fired with a frequency of 1 Hz to 500 Hz.
13. Method according to claim 10,
wherein
depending on the angle of rotation of a drill head of the drilling body a selected part at the bottom of the borehole is fired at.
14. Method for explosive drilling using an explosive with liquid oxygen and, wherein a device according to claim 1 is employed.