1. A photoelectric conversion element comprising:
a first electrode having a porous oxide semiconductor layer which supports a sensitizing dye on a surface thereof and functioning as a photo electrode;
a second electrode disposed so as to oppose the first electrode;
an electrolyte disposed in at least a part of a space between the first electrode and the second electrode;
a collector wiring composed of a conductive material provided in the first electrode; and
a sump portion for the electrolyte provided around the collector wiring, wherein the sump portion is provided between the collector wiring and the porous oxide semiconductor layer.
2. The photoelectric conversion element according to claim 1, wherein an inclined portion is provided on the second electrode in a manner such that the clearance between the first electrode and the second electrode is wider in periphery of the sump portion than the other parts.
3. The photoelectric conversion element according to claim 1, further comprising a protective layer provided around the collector wiring, wherein the sump portion is provided between the protective layer and the porous oxide semiconductor layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic circuit comprising:
a plurality of flash memory cells, wherein:
the plurality of flash memory cells comprises a storage flash cell and a calibration flash cell;
the calibration flash cell is electrically connected to the storage flash cell;
the storage flash cell and calibration flash cell comprise a macro cell;
the storage flash cell is configured and disposed to store data; and
the calibration flash cell is configured and disposed to store a voltage threshold adjustment parameter for the storage flash cell;
a bit line connected to a drain of the calibration flash cell;
an I line, wherein the I line is connected to a source of the calibration flash cell and wherein the I line is connected to a drain of the storage flash cell and wherein the I line is connected to control logic, the control logic configured and disposed to adjust voltage levels of the I line; and
a source line connected to a source of the storage flash cell.
2. The circuit of claim 1, wherein the storage flash cell comprises a multi-level flash memory cell.
3. The circuit of claim 1, wherein the storage flash cell and calibration flash cell are contained within a common memory array.
4. The circuit of claim 1, wherein the storage flash cell is electrically connected in parallel to the calibration flash cell.
5. An electronic circuit comprising:
a plurality of flash memory cells, wherein:
the plurality of flash memory cells comprises a storage flash cell and a calibration flash cell;
the calibration flash cell is electrically connected to the storage flash cell;
the storage flash cell and calibration flash cell comprise a macro cell;
the storage flash cell is configured and disposed to store data; and
the calibration flash cell is configured and disposed to store a voltage threshold adjustment parameter for the storage flash cell, wherein the storage flash cell is electrically connected in series to the calibration flash cell;
a bit line connected to a drain of the storage flash cell;
an I line, wherein the I line is connected to a source of the storage flash cell and wherein the I line is connected to a drain of the calibration flash cell and wherein the I line is connected to control logic, the control logic configured and disposed to adjust voltage levels of the I line; and
a source line connected to a source of the calibration flash cell.
6. The circuit of claim 5, wherein the storage flash cell and calibration flash cell are contained within a common memory array.
7. The circuit of claim 5, wherein the storage flash cell comprises a multi-level flash memory cell.