1. A power semiconductor device comprising:
an output transistor connected between a power supply terminal provided to receive a power supply voltage and an output terminal to be connected with a load;
a load control circuit adapted to feed said gate voltage to said gate of said output transistor, and to stop feeding said gate voltage to said output transistor when short-circuiting of said load occurs; and
a pull-up circuit connected between said power supply terminal and said gate of said output transistor, and adapted to discharge electric charges on said gate of said output transistor, when short-circuiting of said load occurs with a voltage level on said power supply terminal lowered below said power supply voltage.
2. The power semiconductor device according to claim 1, further comprising:
an overcurrent protection circuit monitoring an output current of said output current, configured to output an output shutdown signal to said load control circuit and to provide an electrical connection between said gate of said output transistor and a ground terminal when said output current exceeds a given reference level,
wherein said load control circuit stops feeding said gate voltage to said output transistor in response to said output shutdown signal, and
wherein said pull-up circuit is adapted to discharge electric charges on said gate of said output transistor so as to allow said overcurrent protection circuit to operate, when short-circuiting of said load occurs with said voltage level on said power supply terminal lowered below said power supply voltage.
3. The power semiconductor device according to claim 1, wherein said pull-up circuit includes:
a pull-up transistor connected between said power supply terminal and said gate of said output transistor; and
a diode connected between said pull-up transistor and said gate of said output transistor.
4. The power semiconductor device according to claim 3, wherein said pull-up transistor is an N-channel MOSFET having a source and backgate connected to said power supply terminal and a gate earth-grounded, and
wherein said diode has a cathode connected with a drain of said pull-up transistor and an anode connected with said gate of said output transistor.
5. The power semiconductor device according to claim 4, wherein, when short-circuiting of said load occurs with said voltage level on said power supply terminal lowered below said power supply voltage, causing a decrease in a source-gate voltage of said pull-up transistor, said pull-up transistor discharges said electric charges on said gate of said output transistor by flowing a drain current therethrough to reduce said output current of said output transistor.
6. The power semiconductor device according to claim 4, wherein said pull-up transistor is a depletion type MOS transistor.
7. The power semiconductor device according to claim 2, wherein said overcurrent protection circuit includes:
an overcurrent protection transistor connected between said gate of said output transistor and said ground terminal; and
a monitor circuit monitoring said output current of said output transistor,
wherein said monitor circuit feeds a gate voltage of said overcurrent protection transistor so that said overcurrent protection transistor is turned on when short-circuiting of said load occurs with said voltage level on said power supply terminal lowered below said power supply voltage.
8. The power semiconductor device according to claim 2, wherein said overcurrent protection circuit includes:
an overcurrent protection transistor connected between said gate of said output transistor and said output terminal; and
a monitor circuit monitoring said output current of said output transistor,
wherein said monitor circuit feeds a gate voltage of said overcurrent protection transistor so that said overcurrent protection transistor is turned on when short-circuiting of said load occurs with said voltage level on said power supply terminal lowered below said power supply voltage.
9. The power semiconductor device according to claim 2, wherein said overcurrent protection circuit includes:
a first overcurrent protection transistor connected between said gate of said output transistor and said ground terminal; and
first and second monitor circuits monitoring said output current of said output transistor,
wherein said first and second monitor circuits feeds a gate voltage and a backgate voltage of said first overcurrent protection transistor, respectively, so that said first overcurrent protection transistor is turned off when short-circuiting of said load occurs with said voltage level on said power supply terminal lowered below said power supply voltage, and
wherein a turn-on voltage for said backgate voltage at which said overcurrent protection transistor is turned on is lower than that for said gate voltage, due to an operation of a parasitic bipolar transistor within said first overcurrent protection transistor.
10. The power semiconductor device according to claim 9, wherein said second monitor circuit comprises:
a resistance element connected between said power supply terminal and said ground terminal; and
a second overcurrent protection transistor connected between said resistance element and said ground terminal, and
wherein said parasitic bipolar transistor is allowed to operate due to a connection of a backgate of said first overcurrent protection transistor to a connection node between said resistance element and said second overcurrent protection transistor.
11. The power semiconductor device according to claim 1, wherein said power supply voltage is to be fed from said battery.
12. A system comprising:
a power semiconductor device
a battery feeding a power supply voltage to said power semiconductor device; and
a load receiving an output current from said power semiconductor device,
wherein a power semiconductor device includes:
an output transistor connected between a power supply terminal receiving said power supply voltage and an output terminal connected with said load;
a load control circuit adapted to feed said gate voltage to said gate of said output transistor, and to stop feeding said gate voltage to said output transistor when short-circuiting of said load occurs; and
a pull-up circuit connected between said power supply terminal and said gate of said output transistor, and adapted to discharge electric charges on said gate of said output transistor, when short-circuiting of said load occurs with a voltage level on said power supply terminal lowered below said power supply voltage.
13. A system comprising:
a power semiconductor device
a battery feeding a power supply voltage to said power semiconductor device;
a load receiving an output current from said power semiconductor device; and
a chassis connected to a negative electrode of said battery,
wherein said power semiconductor device includes:
an output transistor connected between a power supply terminal receiving said power supply voltage and an output terminal connected to said load;
a load control circuit connected to a gate of said output transistor; and
a pull-up circuit connected between said power supply terminal and said gate of said output transistor, including:
a pull-up transistor connected to said power supply terminal and said gate of said output transistor; and
a diode connected between said pull-up transistor and said gate of said output transistor,
wherein said pull-up transistor is an N-channel depletion type MOSFET having a source and backgate connected to said power supply terminal and a gate earth-grounded, and
wherein said diode has a cathode connected to a drain of said pull-up transistor and an anode connected to said gate of said output transistor.
14. The system according to claim 13, wherein said chassis and said load are commonly connected to said ground terminal.
15. The system according to claim 12, wherein said pull-up circuit includes:
a pull-up transistor connected between said power supply terminal and said gate of said output transistor; and
a diode connected between said pull-up transistor and said gate of said output transistor.
16. The power semiconductor device according to claim 15, wherein said pull-up transistor is an N-channel MOSFET having a source and backgate connected to said power supply terminal and a gate earth-grounded, and
wherein said diode has a cathode connected with a drain of said pull-up transistor and an anode connected with said gate of said output transistor.
17. The power semiconductor device according to claim 16, wherein said pull-up transistor is a depletion type MOS transistor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A heat-sensitive transfer sheet, comprising a substrate, at least one thermal transfer layer containing a thermally transferable dye and a resin, disposed on one surface of the substrate, and a heat-resistant slipping layer disposed on another surface of the substrate,
wherein said at least one thermal transfer layer contains at least one kind of polymer type releasing agent having a mass-average molecular weight of 5,000 to 100,000 and also having a fluorine-substituted aliphatic group at a side chain of the polymer, and at least one kind of non-polymer type fluorine-system surfactant.
2. The heat-sensitive transfer sheet according to claim 1, wherein the non-polymer type fluorine-system surfactant is a compound represented by the following formula (FS):
wherein A and B each independently represent a fluorine atom or a hydrogen atom; a and b each independently represent an integer of 1 to 6; c and d each independently represent an integer of 4 to 8; x represents 0 or 1; and M represents a cation.
3. The heat-sensitive transfer sheet according to claim 1, wherein the non-polymer type fluorine-system surfactant is a compound represented by the following formula (FS-a):
wherein a, b, c, d, M, and x each have the same meanings as those of formula (FS).
4. The heat-sensitive transfer sheet according to claim 1, wherein the non-polymer type fluorine-system surfactant is a compound represented by the following formula (FS-b):
wherein a1 represents an integer of 2 to 3; c1 represents an integer of 4 to 6; M represents a cation; and x represents 0 or 1.