1. An array substrate of a liquid crystal display device, comprising:
an insulation substrate;
a gate line;
a data line;
a thin film transistor connected to the gate line and the data line;
a common electrode disposed at a pixel area;
a pixel electrode overlapping with the common electrode; and
a common line connected to the common electrode and overlapping with a gap between the common electrode and the data line.
2. The array substrate of claim 1, wherein the common electrode has a plate shape, and
wherein the pixel electrode comprises horizontal parts having a stripe shape and a vertical part disposed between the horizontal parts and connecting the horizontal parts.
3. The array substrate of claim 2, wherein the vertical part connects end portions of the horizontal parts.
4. The array substrate of claim 3, wherein the vertical part is arranged in a straight line.
5. The array substrate of claim 3, wherein the vertical part shifts back and forth from left to right.
6. The array substrate of claim 2, wherein the vertical part crosses the horizontal parts and connects adjacent horizontal parts.
7. The array substrate of claim 6, wherein the vertical part is arranged in a straight line.
8. The array substrate of claim 6, wherein the vertical part shifts back and forth from left to right.
9. The array substrate of claim 1, wherein the common line and the gate line are arranged on substantially the same layer.
10. The array substrate of claim 1, wherein the thin film transistor comprises:
a gate electrode;
an activation layer disposed on the gate electrode and insulated from the gate electrode; and
a source electrode and a drain electrode spaced apart from each other on the activation layer.
11. The array substrate of claim 1, wherein the gate line and the data line comprise at least one metal or alloy of metal selected from the group consisting of molybdenum (Mo), niobium (Nb), copper (Cu), aluminum (Al), chrome (Cr), silver (Ag), and tungsten (W).
12. The array substrate of claim 1, wherein the common line comprises at least one metal or alloy of metal selected from the group consisting of molybdenum (Mo), niobium (Nb), copper (Cu), aluminum (Al), chrome (Cr), silver (Ag), and tungsten (W).
13. The array substrate of claim 1, wherein the common electrode and the pixel electrode comprise a transparent conductive material.
14. The array substrate of claim 13, wherein the transparent conductive material comprises at least one material selected from the group consisting of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
15. A method of manufacturing an array substrate of a liquid crystal display device, comprising:
forming a common electrode at each of a plurality of pixel areas of an insulation substrate;
forming a first metallic pattern comprising a gate line, a gate electrode, and a common line, the common line connected to the common electrode and covering a lateral gap between the common electrode and an adjacent common electrode;
forming a gate insulation layer on the first metallic pattern;
forming an activation layer on the gate insulation layer to overlap with the gate electrode;
forming a second metallic pattern comprising a data line overlapping with the common line and a source electrode and a drain electrode spaced apart from each other on the activation layer;
forming a protective layer on the second metallic pattern; and
forming a pixel electrode on the protective layer.
16. The method of claim 15, wherein the common electrode has as a plate shape, and
the pixel electrode comprises horizontal parts having stripe shapes and a vertical part disposed between adjacent horizontal parts to connect to the adjacent horizontal parts.
17. The method of claim 16, wherein the vertical part connects end portions of the horizontal parts, and
wherein the vertical part is arranged in a straight line.
18. The method of claim 16, wherein the vertical part connects end portions of the horizontal parts, and
wherein the vertical part shifts back and forth from left to right.
19. The method of claim 16, wherein the vertical parts cross the horizontal parts and connect adjacent horizontal parts, and
wherein the vertical part is arranged in a straight line.
20. The method of claim 16, wherein the vertical parts cross the horizontal parts and connect adjacent horizontal parts, and
wherein the vertical part shifts back and forth from left to right.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A process for manufacturing phase change memory cells, comprising:
forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with said heater element; wherein said step of forming said heater element and said phase change storage region comprises:
forming a heater structure and a phase change layer on and in contact with said heater structure; and
defining said phase change layer and said heater structure by subsequent self-aligned etch steps.
2. A process according to claim 1, wherein said step of forming said heater element and said phase change storage region comprises:
depositing a dielectric layer on said wafer;
forming at least a trench in said dielectric layer, said trench being elongated according to a first direction; and
forming said heater structure within said trench.
3. A process according to claim 2, wherein said step of forming said heater structure within said trench includes conformally depositing a heater layer of a resistive material in said trench, said heater layer having a sublithographic thickness.
4. A process according to claim 3, wherein a plurality of phase change memory cells arranged in rows and columns are made, said rows extending according to said first direction, and wherein making each phase change memory cell includes forming a respective selection element in said wafer.
5. A process according to claim 4, wherein one said trench is formed for each row of said phase change memory cells, said trench continuously extending above selection elements aligned in a same row.
6. A process according to claim 4, comprising forming a plurality of trenches, wherein each of said trenches extends above two adjacent rows of said selection elements.
7. A process according to claim 6, wherein said trenches continuously extend in said first direction.
8. A process according to claim 6, wherein forming said heater structures within said trench comprises selectively removing first portions of said heater layer from bottom portions of said trenches, thereby separating second portions of said heater layer form each other, said second portions of said heater layer adhering to side walls of said trenches.
9. A process according to claim 2, comprising the step of depositing a structural layer on said heater structure and forming elongated openings extending across said heater structure in a second direction, transverse to said first direction.
10. A process according to claim 9, wherein said elongated openings include slits having a sublithographic width according to said first direction.
11. A process according to claim 10 wherein said slits extend across all rows in said second direction.
12. A process according to claim 9, wherein forming said phase change storage region comprises filling elongated openings by depositing said phase change layer on said structural layer.
13. A phase change memory cell, comprising:
a heater element and
a storage region of a phase change material on and in contact with said heater element wherein said heater element and said phase change storage region have a same dimension according to a first direction.
14. A memory cell according to claim 13, wherein, at a contact area between said heater element and said storage region, said phase change storage region has a first sublithographic dimension in said first direction, and said heater element has a second sublithographic dimension in a second direction transverse to said first direction.
15. A phase change memory device, comprising:
a plurality of phase change memory cells, wherein each memory cell comprises:
a heater element; and
a storage region of a phase change material on and in contact with said heater element; wherein said heater element and said phase change storage region have a same dimension according to a first direction.
16. A phase change memory device according to 15 wherein at a contact area between said heater element and said storage region, said phase change storage region has a first sublithographic dimension in said first direction, and said heater element has a second sublithographic dimension in a second direction transverse to said first direction.
17. A system comprising:
a processing unit;
an interface coupled to said processing unit; and
a nonvolatile phase change memory device, coupled to said processing unit and including a plurality of phase change memory cells wherein said memory cells comprise:
a heater element;
a storage region of a phase change material on and in contact with said heater element;
wherein said heater element and said phase change storage region have a same dimension according to a first direction.
18. A system according to claim 15, wherein said interface is a wireless interface.
19. A process for manufacturing phase change memory cells comprising:
forming a heater structure above a semiconductor substrate;
depositing an insulating layer above the heater structure;
etching an opening in the insulating layer to expose a portion of the heater structure;
depositing phase change material on the insulating layer such that said phase change material is in contact with the heater structure at the opening;
depositing a barrier layer above the phase change material;
etching the barrier layer to remove a first portion thereof and to leave a second portion thereof; and
using the second portion of the barrier layer as a mask to etch the phase change layer and the heater structure.
20. A process according to 19 wherein said mask is used in etching a mold layer.
21. A process according to 19 wherein said mask layer is used in etching an adhesion layer.