1. A method for retrieving content for a client comprising:
receiving a reference to secure content accessed via a first resource;
editing the reference to the secure content to redirect requests for the secure content to a trusted agent, the edited reference to the secure content including information that identifies the first resource and the secure content of the received reference;
forwarding the edited reference to the client; and
requesting the secure content from the first resource, by the trusted agent on behalf of the client, when the client requests the edited reference.
2. The method of claim 1, wherein the secure content is web content.
3. The method of claim 2, wherein editing the reference to the secure content includes inserting a first predetermined domain in the reference to the secure content.
4. The method of claim 1, further comprising:
returning, in response to domain name lookup requests received from the client for the first predetermined domain, an address of the trusted agent.
5. The method of claim 1, wherein the reference to the secure content is a HyperText Transfer Protocol (HTTPS) link.
6. The method of claim 1, wherein the secure content is accessed via a Secure Socket Layer (SSL) connection.
7. The method of claim 1, wherein the edited reference to the secure content includes all fields of the received reference.
8. The method of claim 1, wherein the trusted agent is implemented as first and second proxy servers in a satellite network.
9. The method of claim 1, further including:
receiving a request from the first resource to store cookies at the client; and
editing domain and path attributes of the request to reference the first resource accessed via the trusted agent.
10. A device for retrieving content for a client comprising:
means for receiving a reference to secure content accessed via a first resource;
means for editing the reference to the secure content to redirect requests for the secure content to a trusted agent, the edited reference to the secure content including information that identifies the first resource;
means for forwarding the edited reference to the client; and
means for requesting the secure content from the first resource, by the trusted agent on behalf of the client, when the client requests the edited reference.
11. The device of claim 10, wherein the secure content is web content.
12. The device of claim 11, wherein the means for editing the reference to the secure content inserts a first predetermined domain in the reference to the secure content.
13. The device of claim 10, wherein the reference to the secure content is a secure HyperText Transfer Protocol (HTTPS) link.
14. The device of claim 10, wherein the secure content is accessed via a Secure Socket Layer (SSL) connection.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode; and
completing auto-refresh operation for the current row for all memory cell array banks prior to updating the current row to a new row for the first time in the self-refresh mode.
2. The method of claim 1, wherein completing an auto-refresh operation for the current row for all memory cell array banks comprises sequencing through all memory cell array banks and performing a refresh operation for the current row in each bank.
3. The method of claim 2, further comprising, during sequencing through all memory cell array banks prior to updating the current row to a new row for the first time in self-refresh mode, clocking refresh operations at a faster rate than the refresh rate used after updating the current row to a new row for the first time in self-refresh mode.
4. The method of claim 1, wherein completing an auto-refresh operation for the current row for all memory cell array banks comprises initiating a simultaneous refresh operation to the current row in all memory cell array banks.
5. The method of claim 4, further comprising after updating the current row to a new row for the first time in self-refresh mode, performing a simultaneous self-refresh operation to the new current row in all memory cell array banks for each subsequent row.
6. The method of claim 5, wherein performing a simultaneous self-refresh operation comprises enabling a bank address signal for each bank during each self-refresh operation.
7. The method of claim 4, wherein performing a simultaneous self-refresh operation comprises enabling a bank address signal for each bank during each self-refresh operation.
8. The method of claim 4, further comprising after updating the current row to a new row for the first time in self-refresh mode, performing sequential self-refresh operations to the memory cell array banks for each subsequent row.
9. The method of claim 1, wherein completing an auto-refresh operation for the current row and all memory cell array banks comprises:
accepting additional external refresh bank addresses after entering self-refresh mode without leaving self-refresh mode, until a refresh operation has been performed for the current row in each memory cell array bank; and
performing self-refresh operations after the current row is updated to a new row for the first time in the self-refresh mode.
10. The method of claim 9, wherein the number of additional external refresh bank addresses accepted after entering self-refresh mode is equal to the number of memory cell array banks.
11. The method of claim 9, wherein the number of additional external refresh bank addresses accepted after entering self-refresh mode is equal to the number of memory cell array banks that have not yet had a refresh operation performed for the current row.
12. The method of claim 1, wherein completing an auto-refresh operation for the current row and all memory cell array banks prior to updating the current row to a new row for the first time in the self-refresh mode comprises initiating a simultaneous refresh operation to the current row in all memory cell array banks that have not yet had a refresh operation performed for the current row.
13. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, sequencing through all memory cell array banks and performing a refresh operation for the current row in each bank; and
subsequently updating the current row to a new row for the first time in the self-refresh mode.
14. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, initiating a simultaneous refresh operation to the current row in all memory cell array banks; and
subsequently updating the current row to a new row for the first time in the self-refresh mode.
15. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, initiating a simultaneous refresh operation to the current row in all memory cell array banks;
subsequently updating the current row to a new row for the first time in the self-refresh mode; and
performing sequential self-refresh operations to the memory cell array banks for each subsequent row.
16. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, accepting additional external refresh bank addresses without leaving self-refresh mode, until a refresh operation has been performed for the current row in each memory cell array bank;
subsequently updating the current row to a new row for the first time in the self-refresh mode; and
performing self-refresh operations after the current row is updated to a new row.
17. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, initiating a simultaneous refresh operation to the current row in all memory cell array banks that have not yet had a refresh operation performed for the current row;
subsequently updating the current row to a new row for the first time in the self-refresh mode; and
performing self-refresh operations after the current row is updated to a new row.
18. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh request;
performing an auto-refresh operation on a current row of a memory cell array bank in response to the external refresh request;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, accepting additional external refresh requests without leaving self-refresh mode, and performing corresponding auto-refresh operations until a refresh operation has been performed for the current row in each memory cell array bank;
subsequently updating the current row to a new row for the first time in the self-refresh mode; and
performing self-refresh operations after the current row is updated to a new row.
19. A method of operating a memory controller, the method comprising:
issuing auto-refresh bank addresses, to a memory unit having n memory cell array banks, in a sequence that addresses all n banks, and then addresses all n banks again, such that the memory unit can sequentially refresh a current row in all n banks according to the auto-refresh bank address sequence before refreshing another row in one of the banks;
issuing a power-down command to the memory unit; and
without waking the memory unit, issuing additional auto-refresh bank addresses to the memory unit to allow the memory unit to complete refresh operations for the current row before beginning self-refresh operations.
20. The method of claim 19, wherein the number of additional auto-refresh bank addresses issued after the power-down command is equal to n.
21. The method of claim 19, wherein the number of additional auto-refresh bank addresses issued after the power-down command is equal to the number of memory cell array banks that have not yet had a refresh operation performed for the current row.
22. A memory system comprising:
at least one memory unit having n memory banks and a bank-addressable auto-refresh operation, the memory unit comprising auto-refresh circuitry that addresses auto-refresh operations to a refresh row in each addressed bank until each of the n banks have been addressed in at least one auto-refresh operation, the memory unit having circuitry for completing refresh operations for the refresh row in each not-yet-addressed bank upon entering a self-refresh mode; and
a controller to assert active commands and supply external refresh bank address signals to the memory unit, the controller having a normal auto-refresh mode that supplies all n bank address signals in n successive auto-refresh operations for a refresh row, and supplies all n bank address signals in the following n successive auto-refresh operations for a next refresh row, wherein the controller can signal the memory unit to enter self-refresh mode without completing n successive auto-refresh operations for a current refresh row.
23. The memory system of claim 22, further comprising an external refresh signal line connected between the memory unit and the controller to allow the controller to initiate auto-refresh operations on the memory unit.
24. The memory system of claim 23, wherein the memory unit responds to auto-refresh operations signaled on the external refresh signal line after entering self-refresh mode, until each bank has been addressed in at least one auto-refresh operation for the refresh row.
25. The memory system of claim 22, further comprising command signal lines connected between the memory unit and the controller, the controller requesting that the memory unit perform active commands, auto-refresh commands, and self-refresh commands by placing appropriate signaling on the command signal lines.
26. A synchronous memory device comprising:
a plurality n of independently addressable memory cell array banks;
a-refresh address generator to specify a current refresh row to all memory cell array is banks;
bank address circuitry to receive an externally supplied bank address for a refresh operation and apply the refresh operation to the memory cell array bank corresponding to the bank address;
a refresh bank address counter to signal the refresh address generator to generate a new refresh row when refresh operations have been addressed to the current refresh row in each of the plurality of memory cell array banks; and
self-refresh circuitry to apply refresh operations to the memory cell array banks in a self-refresh mode, the self-refresh circuitry comprising circuitry to complete refresh operations for the current refresh row in all memory cell array banks upon entering self-refresh mode and before updating the current refresh row to a new row.
27. The memory device of claim 26, wherein the self-refresh circuitry comprises:
a bank address generator to generate a self-refresh bank address in a self-refresh mode; and
a first switch to select either the externally supplied bank address or the self-refresh bank address for a refresh operation.
28. The memory device of claim 27, wherein the first switch selects the self-refresh bank address in a self-refresh mode.
29. The memory device of claim 28, wherein the bank address generator sequentially generates a self-refresh bank address for each memory cell array bank upon entering self-refresh mode, prior to updating the current refresh row.
30. The memory device of claim 28, wherein the bank address generator sequentially generates a self-refresh bank address for each memory cell array bank that has not been addressed in a refresh operation for the current row upon entering self-refresh mode, prior to updating the current refresh row.
31. The memory device of claim 28, further comprising a set circuit to select all memory cell array banks for a first refresh operation upon entering self-refresh mode.
32. The memory device of claim 28, further comprising a set circuit to select all memory cell array banks that have not been addressed in a refresh operation for the current row for a first refresh operation upon entering self-refresh mode.
33. The memory device of claim 27, wherein the first switch selects the self-refresh bank address once the current refresh row is updated to a new row in self-refresh mode.
34. The memory device of claim 33, wherein prior to the first switch selecting the self-refresh bank address in self-refresh mode, the memory device continues to receive externally supplied bank addresses for refresh operations.
35. The memory device of claim 34, wherein the memory device continues to receive externally supplied bank addresses for refresh operations until all memory cell array banks that were not addressed in a refresh operation for the current row prior to entering self-refresh mode have been addressed in a refresh operation.
36. The memory device of claim 34, wherein the memory device receives n externally supplied bank addresses for refresh operations after entering self-refresh mode.
37. The memory device of claim 33, wherein the first switch operates in response to the output of the refresh bank address counter.
38. The memory device of claim 27, the self-refresh clock circuitry further comprising a self-refresh clock generator to supply a refresh clock signal for refresh operations in self-refresh mode, the self-refresh clock generator supplying refresh clock signals at a first rate until refresh operations for the current refresh row are completed for all memory cell banks, and supplying refresh clock signals at a second rate once the current refresh row is updated to a new row.
39. The memory device of claim 38, wherein the self-refresh clock generator comprises an auto refresh clock generator that is enabled upon entry to self-refresh mode and disabled once the current refresh row is updated to a new row, and a self refresh clock generator that is enabled in self-refresh mode once the auto refresh clock generator is disabled, the auto refresh clock generator having an output clock signal at the first rate, the self-refresh clock generator having an output clock signal at the second rate, the self-refresh clock generator having an output stage that ORs the output clock signals of the auto refresh clock generator and the self-refresh clock generator.
40. The memory device of claim 26, wherein the self-refresh circuitry comprises a set circuit to select all memory cell array banks for refresh operations after entering self-refresh mode.
41. The memory device of claim 35, wherein the set circuit comprises a delay circuit to delay a self-refresh clock, a NOR gate to receive the self-refresh clock and the delayed self-refresh clock, and a drive circuit to drive bank address lines for all memory cell array banks in response to the NOR gate output.
42. The memory device of claim 26, wherein the self-refresh circuitry comprises a set circuit to select all memory cell array banks that have not been addressed in a refresh operation for the current row for a first refresh operation upon entering self-refresh mode.