1. A treatment system comprising:
a process chamber, including a process space;
a remote radical generation system coupled to said process chamber and configured to receive process gas and produce radicals from said process gas;
a gas distribution system configured to receive and distribute a flow of said radicals within said process space, wherein said gas distribution system comprises a diffuser having a diffuser inlet coupled to an outlet of said radical generation system and a diffuser outlet coupled to said process space in said process chamber, and wherein said diffuser comprises a substantially conical volume;
a pedestal coupled to said process chamber and configured to support a substrate in said process space of the process chamber and adjust the temperature of said substrate; and
a vacuum pumping system coupled to said process chamber and configured to evacuate said process chamber.
2. The treatment system of claim 1, wherein said gas distribution system further comprises a gas distribution plate coupled to said diffuser at said diffuser outlet, and wherein said gas distribution plate comprises one or more openings there through.
3. The treatment system of claim 2, wherein said gas distribution plate comprises a plurality of openings distributed substantially equally on said gas distribution plate.
4. The treatment system of claim 2, wherein said gas distribution plate comprises a plurality of openings distributed unequally on said gas distribution plate.
5. The treatment system of claim 1, wherein said gas distribution system further comprises:
a diffuser plate located within said diffuser between said diffuser inlet and said diffuser outlet, said diffuser plate comprises a center body substantially aligned with the flow of said radicals from said radical generation system, wherein said flow of said radicals passes through said diffuser around said center body to said process space.
6. The treatment system of claim 5, wherein said center body comprises a disc.
7. The treatment system of claim 5, wherein said center body comprises a conical structure.
8. The treatment system of claim 5, wherein said diffuser plate is located at said diffuser outlet.
9. The treatment system of claim 5, wherein said diffuser plate is located substantially midway between said diffuser inlet and said diffuser outlet.
10. The treatment system of claim 9, wherein said gas distribution system further comprises a gas distribution plate coupled to said diffuser at said diffuser outlet, and wherein said gas distribution plate comprises one or more openings there through.
11. The treatment system of claim 5, wherein said center body is supported by one or more support arms.
12. The treatment system of claim 5, wherein said center body is supported by a gas distribution plate having one or more openings formed in said gas distribution plate between said center body and the outer wall of said diffuser.
13. The treatment system of claim 1, wherein said diffuser comprises a first entrant region proximate said diffuser inlet and a second entrant region proximate said diffuser outlet, and wherein the half angle of said first entrant region is less than the half angle of said second entrant region.
14. The treatment system of claim 13, where the half angle of said first entrant region is less than or equal to approximately 45 degrees.
15. The treatment system of claim 13, where the half angle of said first entrant region is less than or equal to approximately 15 degrees.
16. The treatment system of claim 13, wherein said gas distribution system further comprises a diffuser plate located within said diffuser between said first entrant region and said second entrant region, said diffuser plate comprises a center body substantially aligned with the flow of said radicals from said radical generation system, wherein said flow of said radicals passes through said diffuser around said center body to said process space.
17. The treatment system of claim 16, wherein said gas distribution system further comprises a gas distribution plate coupled to said diffuser at said diffuser outlet, and wherein said gas distribution plate comprises one or more openings there through.
18. The treatment system of claim 16, wherein said center body comprises a disc.
19. The treatment system of claim 16, wherein said center body comprises a conical structure.
20. The treatment system of claim 16, wherein said center body is supported by one or more support arms.
21. The treatment system of claim 13, wherein said gas distribution system further comprises a diffuser plate located within said diffuser at said diffuser outlet, said diffuser plate comprises a center body substantially aligned with the flow of said radicals from said radical generation system, wherein said flow of said radicals passes through said diffuser around said center body to said process space.
22. The treatment system of claim 21, wherein said center body is supported by a gas distribution plate having one or more openings formed in said gas distribution plate between said center body and the outer wall of said diffuser.
23. The treatment system of claim 1, wherein said pedestal comprises one or more grooves formed in an upper surface of said pedestal, and wherein at least one of said one or more grooves extends to an edge of said pedestal.
24. The treatment system of claim 1, wherein said pedestal comprises one or more heating elements, or one or more cooling elements, or a combination thereof, for controlling said temperature of said substrate.
25. The treatment system of claim 1, wherein said pedestal is formed of aluminum having a coating thereon.
26. The treatment system of claim 25, wherein said coating is an anodic layer.
27. The treatment system of claim 25, wherein said coating contains at least one column III element.
28. The treatment system of claim 25, wherein said coating contains at least one element selected from the group consisting of Al2O3, Sc2O3, Sc2F3, YF3, La2O3, Y2O3, and DyO3.
29. The treatment system of claim 1, wherein said gas distribution system is formed of aluminum having a coating thereon.
30. The treatment system of claim 29, wherein said coating is an anodic layer.
31. The treatment system of claim 29, wherein said coating contains at least one column III element.
32. The treatment system of claim 29, wherein said coating contains at least one element selected from the group consisting of Al2O3, Sc2O3, Sc2F3, YF3, La2O3, Y2O3, and DyO3.
33. The treatment system of claim 1, further comprising:
a process gas supply system coupled to said radical generation system, and configured to supply said process gas to said radical generation system.
34. The treatment system of claim 33, wherein said process gas supply system is configured to supply one or more of O2, N2, NO, NO2, N2O, CO, CO2, NH3, NF3, or CF4, or any combination of two or more thereof.
35. The treatment system of claim 1, further comprising:
an edge ring coupled to said process chamber and configured to surround said process space in order to impede the flow of radicals beyond a peripheral edge of said substrate.
36. The treatment system of claim 35, wherein said edge ring comprises a pedestal edge ring coupled to a peripheral edge of said pedestal.
37. The treatment system of claim 1, further comprising:
an edge ring coupled to said process chamber and configured to surround said process space in order to impede the flow of radicals beyond a peripheral edge of said substrate, wherein said edge ring comprises an edge ring coupled to a peripheral edge of said gas distribution system.
38. A treatment system comprising:
a process chamber, including a process space;
a remote radical generation system coupled to said process chamber and configured to receive process gas and produce radicals from said process gas;
a radical delivery system configured to receive and deliver a flow of said radicals within said process space, wherein said radical system comprises a duct having a duct inlet coupled to an outlet of said radical generation system and a duct coupled to a plenum;
a gas distribution plate coupled to an outlet of said plenum and configured to disperse said radicals to the process space;
a pedestal coupled to said process chamber and configured to support a substrate in said process chamber and adjust the temperature of said substrate; and
a vacuum pumping system coupled to said process chamber and configured to evacuate said process chamber.
39. A treatment system comprising:
a process chamber including a process space;
means for generating radicals from the process gas remotely from said process space;
means for delivering said radicals to the process space;
a pedestal coupled to said process chamber and configured to support a substrate in the process chamber and adjust a temperature of the substrate; and
a vacuum pumping system coupled to said process chamber and configured to evacuate said process chamber.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A simultaneous bi-directional data bus comprising:
a simultaneous bi-directional data bus having a characteristic impedance Z0;
a first driver unit and receiver unit connected to a first terminal end of the simultaneous bi-directional data bus;
a second driver unit and receiver unit connected to a second terminal end of the simultaneous bi-directional data bus;
each of the first driver unit and the second driver unit having a sourcing current source and a first resistor connected in parallel between a voltage supply and a terminal end of the simultaneous bi-directional data bus, and a sinking current source and a second resistor connected in parallel between a ground and a terminal end of the simultaneous bi-directional data bus, wherein a substantially higher impedance of each current source relative to a substantially lower impedance of each resistor connected in parallel to the current source provides a relatively constant impedance in each driver unit which substantially matches the characteristic impedance of the simultaneous bi-directional data bus.
2. The simultaneous bi-directional data bus of claim 1 where, in each of the first driver unit and the second driver unit, the first resistor of the sourcing current source and the second resistor of the sinking current source is substantially equal to twice the characteristic impedance of the simultaneous bi-directional data bus.
3. The simultaneous bi-directional data bus of claim 1, wherein the sourcing current sources of each of the first driver unit and the second driver unit are identical sourcing current sources, and the sinking current sources of each of the first driver unit and the second driver unit are identical sinking current sources.
4. The simultaneous bi-directional data bus of claim 1, wherein each driver unit comprises a p side driver and an n side driver which are serially connected between a voltage supply and ground, with the connection between the serially connected drivers being connected to the simultaneous bi-directional data bus, and each driver unit has an output impedance of substantially twice the characteristic impedance of the simultaneous bi-directional data bus so that the total output impedance of each driver unit substantially matches the characteristic impedance of the simultaneous bi-directional data bus.
5. The simultaneous bi-directional data bus of claim 1, wherein each driver unit includes a set of programmable compensation capacitors to compensate for parasitic capacitance and to accelerate transitions to higher speeds.
6. The simultaneous bi-directional data bus of claim 1, wherein each sinking current source includes a pfet device, with its gate coupled to an input, coupled to the power supply, with the pfet device being coupled through first, second and third resistors to ground, with a plurality of programmable pfet devices and series connected compensating capacitors being connected in parallel with the second resistor, and the connection between the first and second resistors being connected to the gate of an nfet device.
7. The simultaneous bi-directional data bus of claim 1, wherein each sinking current source includes a pfet device P0s, with its gate coupled to an input Vin, coupled to the power supply Vcc, with the pfet device being coupled through first, second and third resistors Rgn1, Rgn2 and Rgn3 to ground 0V, with a plurality of programmable pfet devices P1, P2, Pk and series connected compensating capacitors Cn1, Cn2, Cnk being connected in parallel with the second resistor Rgn2, and the connection between the first and second resistors Rgn1, Rgn2 being connected to the gate of an nfet device N0, and the gate-source voltage of the nfet device N0 Vgn=Vcc*Rgn2(Rgn1+Rgn2+Rgn3) when Vin is at logic 0 and P0s is turned on.
8. The simultaneous bi-directional data bus of claim 7, wherein each current source provides the same amount of current I0, and the nfet device N0 and the values of Rgn1, Rgn2 and Rgn3 are chosen to meet the following requirements:
the drain to source current Ids of N0 is I0 when Vgn1=Vcc*Rgn1(Rgn1+Rgn2+Rgn3), and Vgn1\u2212Vthn, the threshold voltage of N0, <(Vcc\u2212I0*Z0)2, so that N0 is at a saturation regionmode when turned on.
9. The simultaneous bi-directional data bus of claim 8, wherein when a logic low is applied to one or more of the gates of P1, P2 . . . Pk, the corresponding capacitors are selected, and when Vin is transiting from a logic high to a logic low, the resistor Rgn2 is shorted by the compensation capacitors.
10. The simultaneous bi-directional data bus of claim 1, wherein each sourcing current source includes an nfet device, having its gate coupled to an input, coupled to ground, with the nfet device being coupled through first, second and third resistors to the power supply, with a plurality of programmable nfet devices and series connected compensating capacitors being connected in parallel with the second resistor, and the connection between the first and second resistors being connected to the gate of a pfet device.
11. The simultaneous bi-directional data bus of claim 1, wherein each sourcing current source includes an nfet device N0s, having its gate coupled to an input Vin, coupled to ground 0V, with the nfet device being coupled through first, second and third resistors Rgp1, Rgp2, Rgp3 to the power supply Vcc, with a plurality of programmable nfet devices N1, N2, Nk and series connected compensating capacitors Cp1, Cp2, Cpk being connected in parallel with the second resistor Rgp2, and the connection between the first and second resistors being connected to the gate of a pfet device P0, and the gate-source voltage of the pfet P0 Vgp=Vcc*Rgp1(Rgp1+Rgp2+Rgp3) when Vin is at logic 1 and N0s is turned on.
12. The simultaneous bi-directional data bus of claim 11, wherein each current source provides the same amount of current I0, and the pfet device P0 and the values of Rgp1, Rgp2 and Rgp3 are chosen to meet the following requirements:
the drain to source current Ids of P0 is I0 when Vgp1=Vcc*Rgp1(Rgp1+Rgp2+Rgp3), and Vgp1\u2212Vthp, the threshold voltage of P0, <(Vcc\u2212I0*Z0)2, so that P0 is at saturation regionmode when turned on.
13. The simultaneous bi-directional data bus of claim 12, wherein when a logic high is applied to one or more of the gates of N1, N2 . . . . Nk, the corresponding capacitors are selected, and when Vin is transiting from a logic low to a logic high, the resistor Rgp2 is shorted by the compensation capacitors.
14. A printed circuit board (PCB) communicating over a simultaneous bi-directional data bus having a characteristic impedance Z0, the PCB having a first driver unit and receiver unit connected to a first terminal end of the simultaneous bi-directional data bus, the driver unit having a sourcing current source and a first resistor connected in parallel between a voltage supply and the first terminal end of the simultaneous bi-directional data bus, and a sinking current source and a second resistor connected in parallel between a ground and the first terminal end of the simultaneous bi-directional data bus, wherein a substantially higher impedance of each current source relative to a substantially lower impedance of each resistor connected in parallel to the current source provides a relatively constant impedance in the first driver unit which substantially matches the characteristic impedance of the simultaneous bi-directional data bus.
15. The PCB of claim 14, the PCB further including thereon:
the simultaneous bi-directional data bus;
a second driver unit and receiver unit connected to a second terminal end of the simultaneous bi-directional data bus;
the second driver unit having a sourcing current source and a first resistor connected in parallel between a voltage supply and a second terminal end of the simultaneous bi-directional data bus, and a sinking current source and a second resistor connected in parallel between a ground and the second terminal end of the simultaneous bi-directional data bus, wherein a substantially higher impedance of each current source relative to a substantially lower impedance of each resistor connected in parallel to the current source provides a relatively constant impedance in the second driver unit which substantially matches the characteristic impedance of the simultaneous bi-directional data bus.
16. The PCB of claim 15, where in each of the first driver unit and the second driver unit, the first resistor of the sourcing current source and the second resistor of the sinking current source is substantially equal to twice the characteristic impedance of the simultaneous bi-directional data bus.
17. The PCB of claim 15, wherein the sourcing current sources of each of the first driver unit and the second driver unit are identical sourcing current sources, and the sinking current sources of each of the first driver unit and the second driver unit are identical sinking current sources.
18. The PCB of claim 15, wherein each driver unit comprises a p side driver and an n side driver which are serially connected between a voltage supply and ground, with the connection between the serially connected drivers being coupled to the simultaneous bi-directional data bus, and each driver unit having an output impedance of twice the characteristic impedance of the simultaneous bi-directional data bus so that the total output impedance of each driver unit matches the characteristic impedance of the simultaneous bi-directional data bus.
19. The PCB of claim 15, wherein each driver unit includes a set of programmable compensation capacitors to compensate for parasitic capacitance and to accelerate transitions to higher speeds.
20. A method of transmitting simultaneous bi-directional data over a bus comprising:
providing a simultaneous bi-directional data bus having a characteristic impedance Z0;
connecting a first driver unit and receiver unit to a first terminal end of the simultaneous bi-directional data bus;
connecting a second driver unit and receiver unit to a second terminal end of the simultaneous bi-directional data bus;
substantially matching the characteristic impedance of each of the first driver unit and the second driver unit to the simultaneous bi-directional data bus by providing each of the first driver unit and the second driver unit with a sourcing current source and a first resistor connected in parallel between a voltage supply and a terminal end of the simultaneous bi-directional data bus, and a sinking current source and a second resistor connected in parallel between a ground and a terminal end of the simultaneous bi-directional data bus, wherein a substantially higher impedance of each current source relative to a substantially lower impedance of each resistor connected in parallel to the current source provides a relatively constant impedance in each driver unit which substantially matches the characteristic impedance of the simultaneous bi-directional data bus.
21. The method of claim 20, including, providing in each of the first driver unit and the second driver unit the first resistor of the sourcing current source and the second resistor of the sinking current source with an impedance equal to substantially twice the characteristic impedance of the simultaneous bi-directional data bus.
22. The method of claim 20, including providing the sourcing current sources of each of the first driver unit and the second driver unit as identical sourcing current sources and the sinking current sources of each of the first driver unit and the second driver unit as identical sinking current sources.
23. The method of claim 20, including providing each driver unit as a p side driver and an n side driver which are serially connected between a voltage supply and ground, coupling the connection between the serially connected drivers to the simultaneous bi-directional data bus, and providing each driver unit with an output impedance of substantially twice the characteristic impedance of the simultaneous bi-directional data bus so that the total output impedance of each driver unit substantially matches the characteristic impedance of the simultaneous bi-directional data bus.
24. The method of claim 20, including providing each driver unit with a set of programmable compensation capacitors to compensate for parasitic capacitance and to accelerate transitions to higher speeds.