1. An intra-field interpolation device for converting an interlaced video signal to a de-interlaced video signal, the device comprising:
a gradient unit receiving an image field for determining a gradient of a first line above a target pixel in the image field and a second line below the target pixel in the image field;
a first pixel difference unit receiving the image field of the interlaced video signal for determining a pair of pixel difference sets on either side of a normal axis of the target pixel in an alternate field of the interlaced video to thereby generate two candidate blending angles for the target pixel, wherein the first pixel difference unit is for generating the two candidate blending angles for the target pixel further according to the gradient;
a second pixel difference unit receiving the image field for determining two reference pixel differences in the image field being along a reference angle on either side of the normal axis of the target pixel;
an angle selection unit being coupled to the first pixel difference unit and the second pixel difference unit for determining an optimal blending angle according to the two candidate blending angles determined by the first pixel difference unit, and the two reference pixel differences determined by the second pixel difference unit; and
a weighted blending unit being coupled to the angle selection unit and receiving the image field for blending a plurality of pixel values in the image field along the optimal blending angle to thereby generate the target pixel in the de-interlaced video signal.
2. The device of claim 1, wherein the second pixel difference unit is for determining the two reference pixel differences being along a 45 degree reference angle on either side of the normal axis of the target pixel.
3. An intra-field interpolation device for converting an interlaced video signal to a de-interlaced video signal, the device comprising:
a first pixel difference unit receiving an image field of the interlaced video signal for determining a pair of pixel difference sets on either side of a normal axis of a target pixel in an alternate field of the interlaced video to thereby generate two candidate blending angles for the target pixel;
a second pixel difference unit receiving the image field for determining two reference pixel differences in the image field being along a reference angle on either side of the normal axis of the target pixel;
an angle selection unit being coupled to the first pixel difference unit and the second pixel difference unit for determining an optimal blending angle according to the two candidate blending angles determined by the first pixel difference unit, and the two reference pixel differences determined by the second pixel difference unit; and
a weighted blending unit being coupled to the angle selection unit and receiving the image field for blending a plurality of pixel values in the image field along the optimal blending angle to thereby generate the target pixel in the de-interlaced video signal;
wherein the angle selection unit includes an angle voting unit for determining the optimal blending angle further according to two previously utilized blending angles; wherein the two previously utilized blending angles correspond to blending angles for two previous pixels that were interpolated prior to the target pixel.
4. The device of claim 1, wherein the weighted blending unit is for performing weighted blending of a plurality of pixels values further along the normal axis to generate the target pixel.
5. The device of claim 4, wherein the weighted blending unit is for performing a two-phase weighting algorithm to interpolate the target pixel; pixel information along the normal axis being weighted according to a first weight, and pixel information along the optimal axis being weighted according to a second weight.
6. The device of claim 1, further comprising a low-pass filter for removing noise from the interlaced video signal.
7. The device of claim 1, wherein the first pixel difference unit is for utilizing a first pixel difference algorithm being substantially different from a second pixel difference algorithm utilized by the second pixel difference unit.
8. An intra-field interpolation method of converting an interlaced video signal to a de-interlaced video signal, the method comprising:
receiving an image field of the interlaced video signal;
utilizing a gradient unit for determining a gradient of a first line above a target pixel in the image field and a second line below the target pixel in the image field;
utilizing a first pixel difference unit for determining a pair of pixel difference sets on either side of a normal axis of the target pixel in an alternate field of the interlaced video to thereby generate two candidate blending angles for the target pixel, wherein the two candidate blending angles for the target pixel are generated further according to the gradient;
utilizing a second pixel difference unit for determining two reference pixel differences in the image field being along a reference angle on either side of the normal axis of the target pixel;
utilizing an angle selection unit for determining an optimal blending angle according to the two candidate blending angles and the two reference pixel differences; and
utilizing a blending unit for blending a plurality of pixel values in the image field along the optimal blending angle to thereby generate the target pixel in the de-interlaced video signal.
9. The method of claim 8, further comprising determining the two reference pixel differences being along a 45 degree reference angle on either side of the normal axis of the target pixel.
10. An intra-field interpolation method of converting an interlaced video signal to a de-interlaced video signal, the method comprising:
receiving an image field of the interlaced video signal;
utilizing a first pixel difference unit for determining a pair of pixel difference sets on either side of a normal axis of a target pixel in an alternate field of the interlaced video to thereby generate two candidate blending angles for the target pixel;
utilizing a second pixel difference unit for determining two reference pixel differences in the image field being along a reference angle on either side of the normal axis of the target pixel;
utilizing an angle selection unit for determining an optimal blending angle according to the two candidate blending angles and the two reference pixel differences, and
further according to two previously utilized blending angles; wherein the two previously utilized blending angles correspond to blending angles for two previous pixels that were interpolated prior to the target pixel; and
utilizing a blending unit for blending a plurality of pixel values in the image field along the optimal blending angle to thereby generate the target pixel in the de-interlaced video signal.
11. The method of claim 8, further comprising performing weighted blending of a plurality of pixels values further along the normal axis to generate the target pixel.
12. The method of claim 11, further comprising performing a two-phase weighting algorithm to interpolate the target pixel; pixel information along the normal axis being weighted according to a first weight, and pixel information along the optimal axis being weighted according to a second weight.
13. The method of claim 8, further comprising removing noise from the interlaced video signal.
14. The method of claim 8, further comprising utilizing a first pixel difference algorithm to determine the pair of pixel difference sets being substantially different from a second pixel difference algorithm utilized to determine the two reference pixel differences.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1: A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type;
a first semiconductor element having a front surface structure in a main surface of the semiconductor substrate;
a second semiconductor element having a front surface structure in the main surface of the semiconductor substrate, the front surface structure of the second semiconductor element being separated from the front surface structure of the first semiconductor element;
a rear surface electrode for the first and second semiconductor elements;
a first semiconductor region of a second conductivity type selectively formed in the main surface of the semiconductor substrate so as to be between the front surface structure of the first semiconductor element and the front surface structure of the second semiconductor element and so as to surround the front surface structure of the first semiconductor element and the front surface structure of the second semiconductor element;
a second semiconductor region of the first conductivity type formed in the main surface of the semiconductor substrate outside the first semiconductor region and separated therefrom; and
at least one trench filled with an insulating layer in the first semiconductor region between the first semiconductor element and the second semiconductor element, respective ends of the at least one trench extending parallel to the main surface out of the first semiconductor region into the second semiconductor region so as to divide the first semiconductor region into a first semiconductor element side and a second semiconductor element side, thereby forming an isolation structure that includes the first semiconductor region between the first semiconductor element and the second semiconductor element and the at least one trench filled with the insulating layer, electrically isolating the front surface structure of the first semiconductor element from the front surface structure of the second semiconductor element.
2. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type;
a first semiconductor element having a front surface structure in a main surface of the semiconductor substrate;
a second semiconductor element having a front surface structure in the main surface of the semiconductor substrate, the front surface structure of the second semiconductor element being separated from the front surface structure of the first semiconductor element;
a rear surface electrode for the first and second semiconductor elements;
a first semiconductor region of a second conductivity type selectively formed in the main surface of the semiconductor substrate so as to be between the front surface structure of the first semiconductor element and the front surface structure of the second semiconductor element and so as to surround the front surface structure of the first semiconductor element and the front surface structure of the second semiconductor element;
a second semiconductor region of the second conductivity type formed in the main surface of the semiconductor substrate outside the first semiconductor region and in contact therewith;
a first trench filled with an insulating layer in the first semiconductor region, surrounding the front surface structure of the first semiconductor element;
a second trench filled with an insulating layer in the first semiconductor region, surrounding the front surface structure of the second semiconductor element, the second trench being separated from the first trench;
a third trench filled with an insulating layer in the first semiconductor region, separated from the first and second trenches and surrounding the first and second trenches so as to divide the first semiconductor region into an inner side and an outer side, thereby forming an isolation structure that includes the first and second trenches and the first semiconductor region between the first semiconductor element and the second semiconductor element, electrically isolating the front surface structure of the first semiconductor element from the front surface structure of the second semiconductor element.
3. The semiconductor device according to claim 2, wherein a width of a portion where the first and third trenches are closest to one another is equal to a width of a portion where the first and second trenches are closest to one another.
4. The semiconductor device according to claim 2, wherein a width of a portion where the second and third trenches are closest to one another is equal to a width of a portion where the first and second trenches are closest to one another.
5. The semiconductor device according to claim 1, wherein a portion of the first semiconductor region that is between the first semiconductor element and the second semiconductor element has a width that withstands at least 60% of a guaranteed maximum breakdown voltage, said portion of the first semiconductor region being completely depleted when the breakdown voltage is reached.
6. The semiconductor device according to claim 2, wherein a portion of the first semiconductor region that is between the first semiconductor element and the second semiconductor element has a width that withstands at least 60% of a guaranteed maximum breakdown voltage, said portion of the first semiconductor region being completely depleted when the breakdown voltage is reached.
7. The semiconductor device according to claim 1, wherein portions of the first semiconductor region located between outer sides of the front surface structure of the first semiconductor element and the second semiconductor region and located between outer sides of the front surface structure of the second semiconductor element and the second semiconductor region form termination structures.
8. The semiconductor device according to claim 2, wherein portions of the first semiconductor region located between outer sides of the front surface structure of the first semiconductor element and the second semiconductor region and located between outer sides of the front surface structure of the second semiconductor element and the second semiconductor region form termination structures.
9. The semiconductor device according to claim 1,
wherein the front surface structure of the first semiconductor element further includes a third semiconductor region of the second conductivity type in the main surface of the semiconductor substrate, the third semiconductor region being in contact with the first semiconductor region and having a higher concentration of impurities than the first semiconductor region, and
wherein the front surface structure of the second semiconductor element further includes a fourth semiconductor region of the second conductivity type in the main surface of the semiconductor substrate, the fourth semiconductor region being in contact with the first semiconductor region and having a higher concentration of impurities than the first semiconductor region,
wherein the semiconductor device further includes:
an interlayer insulating film formed on at least a portion of the third semiconductor region, on at least a portion of the first semiconductor region, and on at least a portion of the fourth semiconductor region;
a first input electrode in contact with the third semiconductor region and an adjacent portion of the first semiconductor region, the first input electrode extending over a portion of the interlayer insulating film;
a second input electrode in contact with the fourth semiconductor region and an adjacent portion of the first semiconductor region, the second input electrode extending over a portion of the interlayer insulating film;
a semiconductor layer of the first conductivity type formed on another main surface of the semiconductor substrate, the semiconductor layer having a higher concentration of impurities than the semiconductor substrate; and
a rear surface electrode in contact with the semiconductor layer.
10. The semiconductor device according to claim 2,
wherein the front surface structure of the first semiconductor element further includes a third semiconductor region of the second conductivity type in the main surface of the semiconductor substrate, the third semiconductor region being in contact with the first semiconductor region and having a higher concentration of impurities than the first semiconductor region, and
wherein the front surface structure of the second semiconductor element further includes a fourth semiconductor region of the second conductivity type in the main surface of the semiconductor substrate, the fourth semiconductor region being in contact with the first semiconductor region and having a higher concentration of impurities than the first semiconductor region,
wherein the semiconductor device further includes:
an interlayer insulating film formed on at least a portion of the third semiconductor region, on at least a portion of the first semiconductor region, and on at least a portion of the fourth semiconductor region;
a first input electrode in contact with the third semiconductor region and an adjacent portion of the first semiconductor region, the first input electrode extending over a portion of the interlayer insulating film;
a second input electrode in contact with the fourth semiconductor region and an adjacent portion of the first semiconductor region, the second input electrode extending over a portion of the interlayer insulating film;
a semiconductor layer of the first conductivity type formed on another main surface of the semiconductor substrate, the semiconductor layer having a higher concentration of impurities than the semiconductor substrate; and
a rear surface electrode in contact with the semiconductor layer.
11. The semiconductor device according to claim 1, wherein a depth of each of said at least one trench is greater than or equal to 1.75 \u03bcm and less than 5.0 \u03bcm.
12. The semiconductor device according to claim 1, wherein a width of each of said at least one trench is greater than or equal to 1.8 \u03bcm and less than 6.0 \u03bcm.
13. The semiconductor device according to claim 1, wherein silicon carbide, gallium nitride, a gallium nitride-based compound, or silicon is used as a semiconductor material of said semiconductor substrate.
14. The semiconductor device according to claim 2, wherein silicon carbide, gallium nitride, a gallium nitride-based compound, or silicon is used as a semiconductor material of said semiconductor substrate.
15. The semiconductor device according to claim 1,
wherein a four-layer hexagonal silicon carbide single crystal is used as a semiconductor material of said semiconductor substrate, and
wherein an impurity dosage of the first semiconductor region is 1.1\xd71013cm2 to 1.75\xd71013cm2.
16. The semiconductor device according to claim 2,
wherein a four-layer hexagonal silicon carbide single crystal is used as a semiconductor material of said semiconductor substrate, and
wherein an impurity dosage of the first semiconductor region is 1.1\xd71013cm2 to 1.75\xd71013cm2.
17. A method of manufacturing a semiconductor device, comprising:
forming a first semiconductor element and a second semiconductor element in a semiconductor substrate of a first conductivity type, the first semiconductor element having a front surface structure in a main surface of the semiconductor substrate, the second semiconductor;
forming a rear surface electrode for the first and second semiconductor elements;
selectively forming a first semiconductor region of a second conductivity type in the main surface of the semiconductor substrate such that the first semiconductor region is located between the front surface structure of the first semiconductor element and the front surface structure of the second semiconductor element as well as surrounding the front surface structure of the first semiconductor element and the front surface structure of the second semiconductor element;
forming a second semiconductor region of the first conductivity type in the main surface of the semiconductor substrate outside the first semiconductor region and separated therefrom; and
forming at least one trench filled with an insulating layer in the first semiconductor region between the first semiconductor element and the second semiconductor element, respective ends of the at least one trench extending parallel to the main surface out of the first semiconductor region into the second semiconductor region so as to divide the first semiconductor region into a first semiconductor element side and a second semiconductor element side, thereby forming an isolation structure that includes said at least one trench filled with the insulating layer and the first semiconductor region between the first semiconductor element and the second semiconductor element, electrically isolating the front surface structure of the first semiconductor element from the front surface structure of the second semiconductor element.