1. A PLI n-bit correction circuit which compares a core header, included in a GFP frame with a fixed payload length, with a predetermined expectation value for each bit so as to calculates the number of inconsistent bits therebetween and which outputs the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number).
2. The PLI n-bit correction circuit according to claim 1, wherein the core header is directly output when the number of inconsistent bits is greater than n.
3. The PLI n-bit correction circuit according to claim 1, wherein a PLI included in the core header is compared with a PLI expectation value, thus calculating the number of inconsistent bits therebetween.
4. The PLI n-bit correction circuit according to claim 1, wherein the core header and the predetermined expectation value are subjected to exclusive-OR operation for each bit and then added together, thus calculating the number of inconsistent bits therebetween.
5. The PLI n-bit correction circuit according to claim 1, wherein a first expectation value and a second expectation value are used as the predetermined expectation value, wherein a first number of inconsistent bits is calculated based on the first expectation value whilst a second number of inconsistent bits is calculated based on the second expectation value, and wherein the minimum number of inconsistent bits, which is either the first or second number of inconsistent bits, is defined as m, which satisfies a condition of n<m2.
6. A GFP Layer 2 synchronization circuit comprising:
a core header drop circuit which extracts a core header from a GFP frame with a fixed payload length;
a PLI n-bit correction circuit which compares the core header with a predetermined expectation value per each bit so as to calculate the number of inconsistent bits therebetween, which outputs the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number), or which directly outputs the core header when the number of inconsistent bits is greater than n;
a Layer 2 synchronization monitor circuit which generates a Layer 2 synchronization signal indicating establishment of Layer 2 synchronization when the PLI n-bit correction circuit consecutively outputs errorless core headers two times or an event of Layer 2 desynchronization when the number of inconsistent bits exceeds n so that the PLI n-bit correction circuit directly outputs the core header without error correction; and
a selector which supplies the Layer 2 synchronization monitor circuit with the output of the PLI n-bit correction circuit when the Layer 2 synchronization signal indicates establishment of Layer 2 synchronization or which supplies the Layer 2 synchronization monitor circuit with the core header output from the core header drop circuit when the Layer 2 synchronization signal indicates the event of Layer 2 desynchronization.
7. A GFP frame transfer device comprising:
a receiver which receives a GFP frame with a fixed payload length;
a core header drop circuit which extracts a core header from the GFP frame;
a PLI n-bit correction circuit which compares the core header with a predetermined expectation value per each bit so as to calculate the number of inconsistent bits therebetween, which outputs the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number), or which directly outputs the core header when the number of inconsistent bits is greater than n;
a Layer 2 synchronization monitor circuit which generates a Layer 2 synchronization signal indicating establishment of Layer 2 synchronization when the PLI n-bit correction circuit consecutively outputs errorless core headers two times or an event of Layer 2 desynchronization when the PLI n-bit correction circuit directly outputs the core header without error correction;
a selector which supplies the Layer 2 synchronization monitor circuit with the output of the PLI n-bit correction circuit when the Layer 2 synchronization signal indicates establishment of Layer 2 synchronization or which supplies the Layer 2 synchronization monitor circuit with the core header output from the core header drop circuit when the Layer 2 synchronization signal indicates the event of Layer 2 desynchronization; and
a GFP frame processing circuit which executes predetermined processing on a payload of the GFP frame dropping the core header when the Layer 2 synchronization signal indicates establishment of Layer 2 synchronization or which discards the GPF frame without performing the predetermined processing on the payload when the Layer 2 synchronization signal indicates the event of Layer 2 desynchronization.
8. A PLI n-bit correction method comprising:
comparing a core header, included in a GFP frame with a fixed payload length, with a predetermined expectation value per each bit;
calculating the number of inconsistent bits therebetween; and
outputting the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number).
9. The PLI n-bit correction method according to claim 8, wherein the core header is directly output when the number of inconsistent bits is greater than n.
10. The PLI n-bit correction method according to claim 8, wherein a PLI included in the core header is compared with a PLI expectation value, thus calculating the number of inconsistent bits therebetween.
11. The PLI n-bit correction method according to claim 8, wherein the core header and the predetermined expectation value are subjected to exclusive-OR operation per each bit and then added together, thus calculating the number of inconsistent bits therebetween.
12. The PLI n-bit correction method according to claim 8, wherein a first expectation value and a second expectation value are used as the predetermined expectation value, wherein a first number of inconsistent bits is calculated based on the first expectation value whilst a second number of inconsistent bits is calculated based on the second expectation value, and wherein the minimum number of inconsistent bits, which is either the first or second number of inconsistent bits, is defined as m, which satisfies a condition of n<m2.
13. A GFP frame transfer method comprising:
extracting a core header from a GFP frame with a fixed payload length;
comparing the core header with a predetermined expectation value for each bit;
calculating the number of inconsistent bits therebetween;
outputting the predetermined expectation value instead of the core header when the number of inconsistent bits is equal to or less than n (where n is a natural number) or directly outputting the core header when the number of inconsistent bits is greater than n;
generating a Layer 2 synchronization signal indicating establishment of Layer 2 synchronization when errorless core headers are consecutively output two times or an event of Layer 2 desynchronization when the number of inconsistent bits exceeds n so that the core header is directly output without error correction; and
performing predetermined processing on a payload of the GFP frame dropping the core header when the Layer 2 synchronization signal indicates establishment of Layer 2 synchronization or discarding the GPF frame without performing predetermined processing on the payload when the Layer 2 synchronization signal indicates the event of Layer 2 desynchronization.
14. The PLI n-bit correction circuit according to claim 2, wherein a PLI included in the core header is compared with a PLI expectation value, thus calculating the number of inconsistent bits therebetween.
15. The PLI n-bit correction circuit according to claim 2, wherein the core header and the predetermined expectation value are subjected to exclusive-OR operation for each bit and then added together, thus calculating the number of inconsistent bits therebetween.
16. The PLI n-bit correction circuit according to claim 2, wherein a first expectation value and a second expectation value are used as the predetermined expectation value, wherein a first number of inconsistent bits is calculated based on the first expectation value whilst a second number of inconsistent bits is calculated based on the second expectation value, and wherein the minimum number of inconsistent bits, which is either the first or second number of inconsistent bits, is defined as m, which satisfies a condition of n<m2.
17. The PLI n-bit correction method according to claim 9, wherein a PLI included in the core header is compared with a PLI expectation value, thus calculating the number of inconsistent bits therebetween.
18. The PLI n-bit correction method according to claim 9, wherein the core header and the predetermined expectation value are subjected to exclusive-OR operation per each bit and then added together, thus calculating the number of inconsistent bits therebetween.
19. The PLI n-bit correction method according to claim 9, wherein a first expectation value and a second expectation value are used as the predetermined expectation value, wherein a first number of inconsistent bits is calculated based on the first expectation value whilst a second number of inconsistent bits is calculated based on the second expectation value, and wherein the minimum number of inconsistent bits, which is either the first or second number of inconsistent bits, is defined as m, which satisfies a condition of n<m2.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of entering an Initialization State in a wireless communication system, characterized in that:
selecting a serving access network;
obtaining synchronization from access network; and
determining if a Redirect Message with a Channel Record is received.
2. The method as claimed in claim 1, characterized in that issuing an InitializationState.Activate command upon entering Initialization State.
3. The method as claimed in claim 1, characterized in that issuing the Channel Record with InitializationState.Activate command if the Redirect Message with Channel Record is received.
4. A computer-readable medium including instructions stored thereon, characterized in that:
a set of instructions for selecting a serving access network;
a set of instructions for obtaining synchronization from access network;
a set of instructions for determining if a Redirect Message with Channel Record is received.
5. An apparatus operable in a wireless communication system, the apparatus characterized in that:
means for selecting a serving access network;
means for obtaining synchronization from an access network;
means for determining if a Redirect Message with a Channel Record is received.
6. The apparatus as claimed in claim 5, characterized in that means for issuing an InitializationState.Activate command upon entering an Initialization State.
7. The apparatus as claimed in claim 5, characterized in that means for issuing the Channel Record with InitializationState.Activate command if the Redirect Message with Channel Record is received.
8. A method of transition to an Idle State, characterized in that:
determining if protocol received an InitializationState.NetworkAcquired indication;
issuing an Initialization State.Deactivate command if the initializationState.NetworkAcquired indication has been received; and
transitioning to the Idle state.
9. A computer-readable medium including instructions stored thereon, characterized in that:
a set of instructions to determine if protocol received an InitializationState.NetworkAcquired indication;
a set of instructions for issuance of an Initialization State.Deactivate command if the InitializationState.NetworkAcquired indication has been received; and
a set of instructions for transitioning to an Idle state.
10. An apparatus operable in a wireless communication system, the apparatus characterized in that:
means to determine if protocol received an InitializationState.NetworkAcquired indication;
means to issue an Initialization State.Deactivate command if InitializationState.NetworkAcquired indication has been received; and
means for transition to Idle state.