1. An X-ray tube comprising:
a cathode emitting electrons;
an anode accelerating emitted electrons;
a target with which accelerated electrons collide and thereby generate X-rays; and
an X-ray shielding member disposed so as to surround a surface of the target facing the cathode, and allowing the electrons to pass through an electron passing hole toward the target,
wherein separately from an opening of the electron passing hole facing the cathode, the X-ray tube has a gas exhaust path allowing communication between the inside and outside of the electron passing hole.
2. The X-ray tube according to claim 1, wherein as the gas exhaust path, a through-hole is formed in the X-ray shielding member.
3. The X-ray tube according to claim 2, wherein the through-hole is formed such that all straight lines imaginarily passing through the through-hole from the position of collision of electrons with the target intersect with the inner wall surface of the through-hole.
4. The X-ray tube according to claim 1, wherein as the gas exhaust path, a gap is formed around an end of the X-ray shielding member facing the anode.
5. The X-ray tube according to claim 4, wherein an auxiliary X-ray shielding member is provided on part of the anode around the X-ray shielding member.
6. The X-ray tube according to claim 1, wherein at least the inner wall surface of the electron passing hole is formed of a conductive material, and the inner wall surface can be controlled at the same potential as the anode.
7. The X-ray tube according to claim 6, wherein the inner wall surface of the X-ray shielding member and the anode are grounded.
8. The X-ray tube according to claim 1, wherein the X-ray tube is a transmission type X-ray tube in which the X-rays are emitted outward from a surface of the target opposite the electron collision surface.
9. The X-ray tube according to claim 1, wherein the cathode is a cold cathode.
10. An X-ray photographing apparatus comprising:
an X-ray tube comprising:
a cathode emitting electrons;
an anode accelerating emitted electrons;
a target with which accelerated electrons collide and thereby generate X-rays; and
an X-ray shielding member disposed so as to surround a surface of the target facing the cathode, and allowing the electrons to pass through an electron passing hole toward the target,
wherein separately from an opening of the electron passing hole facing the cathode, the X-ray tube has a gas exhaust path allowing communication between the inside and outside of the electron passing hole;
an X-ray detecting unit that detects X-rays emitted from the X-ray tube and passing through a subject; and
a control unit that controls the X-ray tube and the X-ray detecting unit in a coordinated manner.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit comprising:
a memory that stores a first task list and a second task list, wherein the first task list includes task instructions, and wherein the second task list includes task instructions;
a first bus coupled to the memory;
a processor adapted to write task instructions into the memory across the first bus;
a first buffer;
a second buffer;
a third buffer;
a second bus coupled to the memory;
a first sub-circuit comprising:
a first processing circuit adapted to read first data from the first buffer, to process the first data thereby generating second data, and to write the second data into the second buffer; and
a first task manager adapted to read a first task instruction of the first task list from the memory across the second bus, to interpret the first task instruction, and to configure the first processing circuit based on a result of the interpreting; and
a second sub-circuit comprising:
a second processing circuit adapted to read the second data from the second buffer, to process the second data thereby generating third data, and to write the third data into the third buffer; and
a second task manager adapted to read a second task instruction of the second task list from the memory across the second bus, to interpret the second task instruction, and to configure the second processing circuit based on a result of the interpreting.
2. The integrated circuit of claim 1, wherein the first task manager is adapted to interpret a plurality of different task instructions, and wherein each of the different task instructions can be executed by the first sub-circuit such that the first processing circuit performs a different processing operation.
3. The integrated circuit of claim 1, further comprising:
a wall clock timer that outputs a sequence of timer count values, wherein the first task instruction read by the first task manager includes a first timer count field, wherein the first processing circuit begins the processing of the first data when a value of the first timer count field substantially equals a first timer count value of the sequence.
4. The integrated circuit of claim 1, further comprising:
a wall clock timer, wherein the first task instruction includes a first timer count value that causes the first task instruction to be executed by the first sub-circuit at a first particular time as indicated by the wall clock timer.
5. The integrated circuit of claim 4, wherein the wall clock timer comprises a task manager, and wherein the task manager of the wall clock timer is adapted to read task instructions across the second bus from a timer task list stored in the memory.
6. The integrated circuit of claim 1, wherein the first task manager includes a first pointer register, wherein the processor is adapted to write a first pointer value into the first pointer register of the first task manager across the second bus, wherein the first pointer value points to location in a circular buffer portion of the memory that contains the first task list.
7. The integrated circuit of claim 6, wherein the first task manager responds to a writing of the first pointer register by reading a task instruction out of the first task list.
8. The integrated circuit of claim 1, wherein the second task list includes a third task instruction, wherein the second task manager reads the third task instruction from the memory across the second bus, interprets the third task instruction, and executes the third task instruction by starting the second processing circuit upon assertion of a signal received from the first processing circuit.
9. The integrated circuit of claim 1, further comprising:
a third sub-circuit comprising:
a third processing circuit adapted to output a signal from the integrated circuit; and
a third task manager adapted to read a third task instruction of a third task list from the memory across the second bus, to interpret the third task instruction, and to configure the third processing circuit based on a result of the interpreting.
10. The integrated circuit of claim 1, further comprising:
a third sub-circuit comprising:
a data mover engine; and
a third task manager adapted to read a third task instruction of a third task list from the memory across the second bus, to interpret the third task instruction, and to configure the data mover engine based on a result of the interpreting.
11. The integrated circuit of claim 1, wherein the second bus comprises:
a first sub-bus that couples the processor to pointer registers in the first task manager and the second task manager, wherein the processor writes pointer values across the first sub-bus into the pointer registers; and
a second sub-bus that couples the memory to the first task manager and to the second task manager, wherein the first and second task mangers read task instructions from the memory across the second sub-bus.
12. The integrated circuit of claim 1, wherein the memory, the first bus, and the processor together form a tightly coupled memory (TCM) system.
13. The integrated circuit of claim 1, wherein the memory is accessible by the processor via the first bus with a smaller memory access latency than the memory is accessible via the second bus by the first and second task managers.
14. The integrated circuit of claim 1, wherein the first and second processing circuits are dedicated hardware circuits that do not fetch instructions.
15. The integrated circuit of claim 1, wherein the first task instruction includes a source address field, and a destination address field, wherein a source address value in the source address field indicates a source location in the first buffer, and wherein a destination address value in the destination address field indicates a destination location in the second buffer.
16. The integrated circuit of claim 1, wherein the processor writes a third task instruction into the first task list while the first sub-circuit is executing the first task instruction.
17. The integrated circuit of claim 1, wherein the first sub-circuit reads a push task instruction from the first task list and executes the push task instruction, wherein execution of the push task instruction by the first sub-circuit causes the first sub-circuit to write information into the memory across the second bus.
18. An integrated circuit comprising:
a Tightly Coupled Memory (TCM) system comprising a processor that is tightly coupled to a memory via a first bus, wherein the memory stores a plurality of task lists;
a timer; and
a plurality of sub-circuits, wherein each sub-circuit reads task instructions via a second bus from a task list that corresponds to the sub-circuit and executes the task instructions, wherein the task lists include a push task instruction that when executed by a sub-circuit causes information to be written by the sub-circuit into the memory, wherein the task lists include a configuration task instruction that when executed by a sub-circuit causes the sub-circuit to be configured in a particular way determined by the configuration task instruction, wherein the task lists include a timestamp task instruction that contains a timer count field, wherein execution of the timestamp task instruction is started by a sub-circuit at a time indicated by a timer count value in the timer count field, and wherein the task lists include a hardware signal event task instruction, wherein execution of the hardware signal event task instruction is started by a sub-circuit upon assertion of a signal generated by another sub-circuit.
19. A method comprising:
storing a first task list and a second task list in a memory, wherein a processor, a first bus, and the memory form a Tightly Coupled Memory (TCM) system;
a first sub-circuit reading a first task instruction of the first task list from the memory across a second bus;
the first sub-circuit performing a first operation indicated by the first task instruction;
a second sub-circuit reading a second task instruction of the second task list from the memory across the second bus; and
the second sub-circuit performing a second operation indicated by the second task instruction, wherein the processor, the first bus, the second bus, the memory, the first sub-circuit and the second sub-circuit are parts of an integrated circuit.
20. The method of claim 19, wherein the first operation involves the first sub-circuit writing data into a buffer, and wherein the second operation involves the second sub-circuit reading the data out of the buffer.
21. The method of claim 20, wherein the first task instruction includes a destination address field, wherein a destination address value in the destination address field indicates a location in the buffer where the first sub-circuit writes the data.
22. The method of claim 20, wherein the second task instruction includes a source address field, wherein a source address value in the source address field indicates a location in the buffer from which the second sub-circuit reads the data.
23. The method of claim 19, further comprising:
storing a timestamp task instruction in the memory in the first task list, wherein the timestamp task instruction has a timer count field, wherein execution of the timestamp task instruction by the first sub-circuit is started at a time indicated by a value in the timer count field.
24. The method of claim 19, further comprising:
storing a push task instruction in the first task list, wherein an execution of the push task instruction by the first sub-circuit results in the first sub-circuit writing information across the second bus into the memory.
25. An apparatus comprising:
a memory that stores a first task list and a second task list;
a processor that is tightly coupled to the memory via a first bus;
a second bus;
first means for reading task instructions of the first task list out of the memory across the second bus and for performing first operations indicated by task instructions of the first task list, wherein the first means performs the first operations without fetching any instruction other than task instructions of the first task list; and
second means for reading task instructions of the second task list out of the memory across the second bus and for performing second operations indicated by task instructions of the second task list, wherein the second means performs the second operations without fetching any instruction other than task instructions of the second task list.
26. The apparatus of claim 25, further comprising:
a buffer, wherein the first means writes data into the buffer at locations indicated by a field in a task instruction of the first task list, and wherein the second means reads the data out of the buffer from locations indicated by a field in a task instruction of the second task list.
27. The apparatus of claim 25, wherein the processor is a processor taken from the group consisting of: a multi-core processor, and a multi-threaded processor.
28. A computer program product, comprising:
computer-readable medium comprising:
a first task list for causing a first sub-circuit to perform a first set of operations indicated by task instructions in the first task list, wherein the first sub-circuit reads the task instructions from the computer-readable medium across a second bus;
a second task list for causing a second sub-circuit to perform a second set of operations indicated by task instructions in the second task list, wherein the second sub-circuit reads the task instructions from the computer-readable medium across the second bus; and
code for causing a processor to maintain the first and second task lists in the computer-readable medium across a first bus.
29. The computer program product of claim 28, wherein the first and second task lists include timestamp task instructions that include timer count fields, wherein the first and second task lists also include push task instructions that cause information to be written by sub-circuits into the computer-readable medium, and wherein the first and second task lists include task instructions that include source address fields and destination address fields.
30. The computer program product of claim 28, wherein the computer-readable medium includes an amount of program memory that stores program code executed by the processor and further includes a cache memory coupled to the processor, wherein the first and second task lists are stored in the cache memory.