1. An improved trocar of the type including a fixed-radius tubular element having a trocar valve at a proximal end thereof, wherein the improvement comprises: a plurality of tubular elements each having a different fixed diameter and means for detachably securing the trocar valve thereto; and means defining a radially expandable axial lumen for selectively receiving and conforming to any of said plurality of tubular elements, whereby said defining means is percutaneously introducible to provide an access lumen for selectively introducing and interchanging said tubular elements into said access lumen of said defining means, wherein the trocar valve is selectively attached to said tubular element after said tubular element has been introduced into said access lumen.
2. An improved trocar as in claim 1, wherein the defining means comprises an elongate radially expandable tubular braid and means at a distal end of the braid for puncturing tissue as the braid is percutaneously advanced.
3. An improved trocar as in claim 2, wherein the puncturing means comprises an elongate penetrating element having a sharpened distal tip and being removably received within an axial lumen of the elongate radially expandable tubular braid.
4. An improved trocar as in claim 3, wherein each tubular element includes a rod received in an axial lumen thereof, wherein the rod has tapered distal end which extends distally from a distal end of the tubular element to facilitate insertion into the axial lumen of the elongate radially expandable tubular braid.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A microcontroller-implemented method, comprising:
determining a mode of a microcontroller; and
if the mode is a compatibility mode, modifying a clock source of the microcontroller to increase instruction execution time.
2. The method of claim 1, where modifying further comprises:
selecting one or more scaling factors or wait state factors; and
applying the one or more scaling factors or wait state factors to the clock source.
3. The method of claim 1, where the one or more scale factors or wait state factors are functions of a current instruction.
4. The method of claim 1, where the one or more scale factors or wait state factors are a constant value.
5. The method of claim 1, where the one or more scale factors or wait state factors are based on an architecture of the microcontroller.
6. The method of claim 1, where the instruction execution time is increased based on the formula T2(I)=T1(I)*S(I)+W(I), where T1 is an instruction execution time for a first microcontroller mode and T2 is an instruction execution time for a second microcontroller mode, I is a current instruction, and S(I) is a scale factor and W(I) is a wait cycle associated with the instruction I.
7. The method of claim 1, where the instruction execution time is increased based on the formula T2(I)=((T1(I)+A(I))*B(I)+C(I))*D, where T1 is an instruction execution time for a first microcontroller mode and T2 is an instruction execution time for a second microcontroller mode, I is a current instruction, D is a divider adjustment representing a quantity adjustment provided by a clock divider, A(I) represents a number of wait states, each wait state scaled by a wait scaling factor B(I) or the divider adjustment D, and C(I) is a further adjustment.
8. The method of claim 7, further comprising:
prescaling the clock source by the factor D prior to modifying the clock source.
9. The method of claim 1, where modifying instruction execution time includes gating or dividing the clock source.
10. A microcontroller-implemented method, comprising:
obtaining a first instruction;
executing the instruction in accordance with a first mode, including executing the first instruction over a first instruction execution time;
obtaining a second instruction; and
executing the second instruction in accordance with a second mode, including executing the second instruction over a second instruction execution time, where the first instruction and the second instruction are the same, and the second instruction execution time is longer than the first instruction execution time.
11. The method of claim 10, where executing the second instruction in accordance with a second mode includes gating or dividing a clock source.
12. The method of claim 10, where executing the second instruction in accordance with a second mode comprises:
selecting one or more scaling factors or wait state factors; and
applying the one or more scaling factors or wait state factors to a clock source of the microcontroller.
13. The method of claim 10, where the one or more scale factors or wait state factors are functions of a current instruction.
14. The method of claim 10, where the one or more scale factors or wait state factors are a constant value.
15. The method of claim 10, where the one or more scale factors or wait state factors are based on an architecture of the microcontroller.
16. The method of claim 10, where the second instruction execution time is increased from the first instruction execution time based on the formula T2(I)=T1(I)*S(I)+W(I), where T1 is the first instruction execution time for the first mode and T2 is a second instruction execution time for the second mode, I is a current instruction, and S(I) is a scale factor and W(I) is a wait cycle associated with the instruction I.
17. The method of claim 10, where the second instruction execution time is increased based on the formula T2(I)=((T1(I)+A(I))*B(I)+C(I))*D, where T1 is the first instruction execution time for the first mode and T2 is the second instruction execution time for the second mode, I is a current instruction, D is a divider adjustment representing a quantity adjustment provided by a clock source divider, A(I) represents a number of wait states, each wait state scaled by a wait scaling factor B(I) or the divider adjustment D, and C(I) is a further adjustment.
18. A microcontroller with compatibility mode, comprising:
an instruction register operable for storing an instruction;
a clock control operable for modifying a clock source if the microcontroller is in compatibility mode; and
a processor operable for executing the instruction using the modified clock source.
19. The microcontroller of claim 18, if the microcontroller is not in compatibility mode, the processor is operable for executing the instruction using an unmodified clock source.
20. The microcontroller of claim 18, further comprising:
a clock divider operable for dividing the clock source prior to the clock control modifying the clock source.
21. The microcontroller of claim 18, further comprising:
a mode selector operable for selecting compatibility mode.
22. The microcontroller of claim 18, where the clock control includes a finite state machine that is operable to modify the clock source using clock division or clock gating to increase execution time of the instruction.
23. The microcontroller of claim 18, further comprising:
a decoder operable for providing values of instruction dependent factors used to modify the execution time of the instruction.
24. The microcontroller of claim 23, where the execution time of the instruction is increased based on the formula T2(I)=T1(I)*S(I)+W(I), where T1 is a first instruction execution time for standard mode and T2 is a second instruction execution time for compatibility mode, I is a current instruction, and S(I) and W(I) are the instruction dependent factors.
25. The microcontroller of claim 23, where the execution time of the instruction is increased based on the formula T2(I)=((T1(I)+A(I))*B(I)+C(I))*D, where T1 is a first instruction execution time for standard mode and T2 is the second instruction execution time for compatibility mode, I is a current instruction, D is a divider adjustment representing a quantity adjustment provided by a clock source divider, A(I) represents a number of wait states, each wait state scaled by a wait scaling factor B(I) or the divider adjustment D, and C(I) is a further adjustment.