1. A method for detecting a prion protein in a sample, andor removing a prion protein from a sample, which method comprises contacting the sample with a compound of formula (I)
wherein
R3 is hydrogen or an aryl group substituent or R3 is a solid support optionally attached via a spacer;
Z represents an oxygen atom, a sulfur atom or NR4;
Y represents an oxygen atom, a sulfur atom or NR5;
wherein R4 and R5, which may be the same or different, represent hydrogen, optionally substituted alkyl containing 1 to 6 carbon atoms, optionally substituted phenyl, optionally substituted benzyl or optionally substituted \u03b2-phenylethyl; and
X1 and X2 both represent a nitrogen atom;
R1 represents a group \u2014(CH2)m-Q1, wherein m is from 0 to 7, and Q1 represents \u2014NR11R12, in which R11 and R12, together with the nitrogen atom to which they are attached, form an optionally substituted heterocycloalkyl group, and
R2 represents a group \u2014(CH2)n-Q2, wherein n is from 0 to 7, and Q2 represents \u2014CR21R22R23 or \u2014NR21R22, in which R23 represents hydrogen, alkyl, cycloalkyl or heterocyclo-alkyl, and R21 and R22, together with the carbon or nitrogen atom to which they are attached, form an optionally substituted cycloalkyl or optionally substituted heterocycloalkyl group;
wherein the compound has affinity for binding the prion protein.
2. A compound of formula (I)
wherein
R3 is hydrogen or an aryl group or R3 is a solid support optionally attached via a spacer;
Z represents NH;
Y represents NH;
X1 and X2 both represent a nitrogen atom;
R1 represents a group \u2014(CH2)m-Q1, wherein m is 2, and Q1 represents
piperidyl or piperazinyl, and
R2 represents a group \u2014(CH2)n-Q2, wherein n is 0 or 2, and Q2 represents 1-piperidyl or adamantyl.
3. A pharmaceutical composition comprising:
a compound according to claim 2, wherein R3 is hydrogen or an aryl group substituent; and
a pharmaceutically acceptable carrier.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A reconfigurable vector processor comprising:
a plurality of processor units, each comprising:
a control unit for decoding instructions and generating control signals;
a scalar unit for processing instructions on scalar data; and
a vector unit for processing instructions on vector data based on the generated control signals; and
a vector control selector for selectively providing control signals generated by one of the plurality of processor units to a vector unit associated with a different processor unit of the plurality of processor units.
2. The reconfigurable vector processor of claim 1, wherein the vector control selector comprises a vector control multiplexer associated with a first processor unit of the plurality of processor units for selectively coupling the vector unit of the first processor unit to the control unit of the first processor unit or to a control unit of a second processor unit of the plurality of processor units to selectively provide the one or more control signals generated by the first processor unit or the second processor unit to the vector unit of the first processor unit.
3. The reconfigurable vector processor of claim 1, wherein the vector control selector comprises a crossbar switch for receiving a plurality of respective control signals from one or more of the plurality of processor units and selectively providing one or more of the received plurality of respective control signals to the respective vector units of one or more processor units of the plurality of processor units.
4. The reconfigurable vector processor architecture of claim 1, further comprising a vector data connector for selectively coupling the vector unit of one processing unit to the vector unit of a processing unit providing the control signals.
5. The reconfigurable vector processor of claim 1, further comprising a plurality of vector control selectors, each vector control selector comprising a vector control multiplexer associated with a respective processor unit of the plurality of processor units.
6. The reconfigurable vector processor of claim 1, wherein the respective control units of one or more processor units, herein after referred to as master units, are coupled to the vector control multiplexer associated with a different processor unit.
7. The reconfigurable vector processor of claim 6, wherein one or more of the master units comprise a vector control multiplexer for selectively coupling the vector unit to the control unit of another master unit.
8. The reconfigurable vector processor of claim 1, wherein the scalar processor of each of the plurality of processor units can perform arithmetic, logical and shift operations.
9. The reconfigurable vector processor of claim 1 wherein each of the plurality of processor units further comprises an address generation unit component for generating the address of the next instruction to be executed by the processor unit.
10. The reconfigurable vector processor of claim 1, wherein the scalar processor of each of the plurality of the processor units can operate concurrently with their respective vector units.
11. The reconfigurable vector processor of claim 1, wherein the scalar processor of each of the processor units can operate autonomously from their respective vector units.
12. The reconfigurable vector processor of claim 1, wherein one or more of the plurality of processor units each further comprise one or more data multiplexers for selectively coupling the vector units of the one or more processor units together.
13. The reconfigurable vector processor of claim 1, wherein each vector unit comprises a plurality of computational units (CUs) each for processing data of a defined bit length.
14. The reconfigurable vector processor of claim 13, wherein each CU is configured to perform add and shift operations on received data.
15. The reconfigurable vector processor of claim 13, wherein each CU comprises:
a data register;
a plurality of bypass multiplexers coupled to the data register;
an arithmetic logic unit coupled to outputs of the plurality of bypass multiplexers;
a multiplication unit coupled to the outputs of the plurality of bypass multiplexers;
a loadstore unit coupled to the outputs of the plurality of bypass multiplexers and a memory; and
a moveshift unit coupled to the outputs of the plurality of bypass multiplexers and one or more other computation units.
16. A method of processing data using a reconfigurable vector processor comprising two or more processing units, each with a vector unit, the method comprising:
configuring the reconfigurable vector processor to provide a vector unit of a first size for processing vector data of the first size;
executing one or more instructions using the vector unit of the first size to process vector data of the first size;
reconfiguring the reconfigurable vector processor to change the size of the vector unit to a second size; and
executing one or more instructions using the vector unit of the second size to process vector data of the second size.
17. The method of claim 16, wherein configuring and reconfiguring the size of the vector unit comprises:
generating control signals for controlling the vector unit of a first processing unit; and
providing the generated control signals to the vector unit of the first processing unit and the vector unit of a second processing unit to provide a vector unit with a total size of the sum of the individual vector units of the first and second processing unit.
18. The method of claim 16, wherein configuring the size of the vector unit comprises:
providing appropriate control signals to one or more components of the reconfigurable vector processor comprising a vector control multiplexer, or data multiplexers.
19. The method of claim 16, further comprising:
executing instructions using one or more scalar processors of the reconfigurable vector processor when executing instructions using the vector unit.
20. The method of claim 16, further comprising:
configuring the reconfigurable vector processor to provide one or more additional vector units for processing vector data.