1. An organic light emitting display device comprising:
a substrate having a pixel region and a transparent region;
a semiconductor device disposed on the substrate;
an insulation layer disposed on the semiconductor device, the insulation layer including an inclined structure;
a first electrode disposed on the insulation layer;
a pixel defining layer disposed on the insulation layer and the first electrode, the pixel defining layer having a pixel opening exposing the first electrode positioned on the inclined structure;
to an organic light emitting layer disposed on the exposed first electrode and the pixel defining layer; and
a second electrode disposed on the organic light emitting layer and the pixel defining layer,
wherein light generated from the organic light emitting layer is directed in different directions by the inclined structure.
2. The organic light emitting display device of claim 1, wherein the inclined structure includes an upper face of the insulation layer having portions inclined by different inclination angles relative to the substrate.
3. The organic light emitting display device of claim 2, wherein a first portion of the upper face of the insulation layer is parallel to an upper surface of the substrate, and a second portion of the upper face of the insulation layer is inclined toward the upper surface of the substrate.
4. The organic light emitting display device of claim 3, wherein the second portion of the upper face of the insulation layer has an inclination angle of about 30\xb0 to about 60\xb0 with respect to the upper surface of the substrate.
5. The organic light emitting display device of claim 4, wherein a first portion of the first electrode on the first portion of the upper face of the insulation layer is parallel to the upper surface of the substrate, and a second portion of the first electrode on the second portion of the upper face of the insulation layer has an inclination angle substantially identical to the inclination angle of the second portion of the upper face.
6. The organic light emitting display device of claim 5, wherein a first portion of the organic light emitting layer on the first portion of the first electrode is parallel to the upper surface of the substrate, and a second portion of the organic light emitting layer on the second portion of the first electrode has an inclination angle substantially identical to the inclination angle of the second portion of the first electrode.
7. The organic light emitting display device of claim 3, wherein the organic light emitting layer extends onto a sidewall of the pixel opening.
8. The organic light emitting display device of claim 3, wherein the organic light emitting display device is a top emission type.
9. The organic light emitting display device of claim 2, wherein a first portion of the upper face of the insulation layer is parallel to an upper surface of the substrate, and a second the upper face of the insulation layer is inclined away from the upper surface of the substrate.
10. The organic light emitting display device of claim 9, wherein the second the upper face of the insulation layer has an inclination angle of about 120\xb0 to about 150\xb0 with respect to the upper surface of the substrate.
11. The organic light emitting display device of claim 9, wherein the organic light emitting display device is a bottom emission type.
12. The organic light emitting display device of claim 1, further comprising an opening provided through the insulation layer and the pixel defining layer in the transparent region, wherein openings of adjacent pixels are symmetrically arranged each other.
13. The organic light emitting display device of claim 1, wherein a first portion of a sidewall of the pixel opening has an inclination angle greater than an inclination angle of a second portion of the sidewall of the pixel opening.
14. The organic light emitting display device of claim 13, wherein a ratio between the inclination angle of the first portion and the inclination angle of the second portion is in a range of about 1.0:0.5 to about 1.0:1.7.
15. A method of manufacturing an organic light emitting display device, comprising:
providing a substrate having a pixel region and a transparent region;
forming a semiconductor device on the substrate;
forming an insulation layer including an inclined structure on the semiconductor device;
forming a first electrode on the insulation layer;
forming a pixel defining layer on the insulation layer and the first electrode, the pixel defining layer having a pixel opening exposing the first electrode positioned on the inclined structure;
forming an organic light emitting layer on the exposed first electrode and the pixel defining layer; and
forming a second electrode on the organic light emitting layer and the pixel defining layer.
16. The method of claim 15, wherein the inclined structure is formed in a configuration to cause light generated from the organic light emitting layer to be directed in different directions.
17. The method of claim 15, wherein forming the insulation layer includes:
forming the insulation layer on the substrate to cover the semiconductor device;
pressing the insulation layer using a mold having a profile opposed to the inclined structure; and
curing the insulation layer.
18. The method of claim 15, wherein forming the insulation layer includes:
forming the insulation layer on the substrate to cover the semiconductor device; and
partially removing the insulation layer using a mask having mask patterns disposed at different distances.
19. The method of claim 15, further comprising forming an opening by partially removing the pixel defining layer and the insulation layer in the transparent region, wherein openings of adjacent pixels are symmetrically arranged with each other.
20. The method of claim 19, wherein the organic light emitting layer is formed to extend onto a sidewall of the pixel defining layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Circuitry for use with a general purpose performance counter (\u201cGPPC\u201d) connected to a bus carrying a plurality of encoded state coverage signals indicative of test coverage in a logic design, said circuitry for decoding and capturing coverage information, comprising:
a selection circuit operating to select said plurality of encoded state coverage signals from a multi-bit event signal carried on said bus;
a line decoder operating to decode said plurality of encoded state coverage signals into N one-hot signals, wherein each one-hot signal is asserted when a corresponding state in said logic design is covered during a test; and
a capture circuit coupled to said line decoder for capturing said N one-hot signals.
2. The circuitry as recited in claim 1, wherein said capture circuit comprises:
an OR logic block for bit-wise ORing said N one-hot signals with an N-bit mask value stored in a register block, said OR logic block operating to generate an N-bit output; and
a Multiplexer (MUX) block operating to select said N-bit output from said OR logic block under control of at least one control signal, wherein said N-bit output is operable to be stored into said register block when selected by said MUX block.
3. The circuitry as recited in claim 2, wherein said OR logic block comprises N 2-input OR gates.
4. The circuitry as recited in claim 2, wherein said MUX block comprises N MUX elements, each for selecting a particular bit of said N-bit output.
5. The circuitry as recited in claim 2, wherein said MUX block comprises N MUX elements, each operating responsive to two control signals for selecting among four MUX inputs, including a particular bit of said N-bit output.
6. The circuitry as recited in claim 5, wherein one of said MUX inputs comprises a value stored in a control status register (CSR).
7. The circuitry as recited in claim 5, wherein one of said MUX inputs comprises said mask value stored in said register block.
8. The circuitry as recited in claim 5, wherein one of said MUX inputs comprises a fixed binary 0 value.
9. The circuitry as recited in claim 1, wherein N is 80.
10. A method of capturing state coverage information in a logic design, comprising:
encoding state coverage information generated when said logic design is exercised under test onto a segment of a bus connected to a general purpose performance counter (\u201cGPPC\u201d);
selecting said segment of said bus for processing;
decoding said segment of said bus into N one-hot signals, wherein each one-hot signal is asserted when a corresponding state in said logic design has been covered during test;
bit-wise ORing said N one-hot signals with an N-bit mask value stored in a register block for generating an N-bit output; and
selecting said N-bit output by a Multiplexer (MUX) block operating under control of at least one control signal, wherein said N-bit output is operable to be stored into said register block when selected by said MUX block.
11. The method of capturing state coverage information in a logic design as recited in claim 10, wherein said bit-wise ORing operation is performed by an OR logic block comprising N 2-input OR gates.
12. The method of capturing state coverage information in a logic design as recited in claim 10, wherein said selecting of said N-bit output is performed by a MUX block comprising N MUX elements, each operating responsive to two control signals for selecting among four MUX inputs, including a particular bit of said N-bit output.
13. The method of capturing state coverage information in a logic design as recited in claim 12, wherein one of said MUX inputs comprises a value stored in a control status register (CSR).
14. The method of capturing state coverage information in a logic design as recited in claim 12, wherein one of said MUX inputs comprises said mask value stored in said register block.
15. The method of capturing state coverage information in a logic design as recited in claim 12, wherein one of said MUX inputs comprises a fixed binary 0 value.
16. The method of capturing state coverage information in a logic design as recited in claim 10, wherein N is 80.
17. A system for capturing state coverage information in a logic design, comprising:
means for encoding state coverage information generated when said logic design is exercised under test onto a segment of bus connected to a general purpose performance counter (\u201cGPPC\u201d);
means for selecting said segment of said bus for processing;
means for decoding said segment of said bus into N one-hot signals, wherein each one-hot signal is asserted when a corresponding state in said logic design has been covered during test;
means for generating an N-bit output based on a logic operation between said N one-hot signals and an N-bit mask value stored in a register block; and
a Multiplexer (MUX) block operating to select said N-bit output under control of at least one control signal, wherein said N-bit output is operable to be stored into said register block when selected by said MUX block.
18. The system for capturing state coverage information in a logic design as recited in claim 17, wherein said means for generating said N-bit output comprises an OR logic block that includes N 2-input OR gates for performing a bit-wise logic OR operation.
19. The system for capturing state coverage information in a logic design as recited in claim 17, wherein said MUX block comprises N MUX elements, each operating in response to two control signals for selecting among four MUX inputs, including a particular bit of said N-bit output.
20. The system for capturing state coverage information in a logic design as recited in claim 19, wherein one of said MUX inputs comprises a value stored in a control status register (CSR).
21. The system for capturing state coverage information in a logic design as recited in claim 19, wherein one of said MUX inputs comprises said mask value stored in said register block.
22. The system for capturing state coverage information in a logic design as recited in claim 19, wherein one of said MUX inputs comprises a fixed binary 0 value.
23. The system for capturing state coverage information in a logic design as recited in claim 17, wherein N is 80.