1-91. (canceled)
92. A method for switching a power bipolar semiconductor device which includes both an n-type emittercollector region, and also a p-type base contact region, on both first and second surfaces of a p-type semiconductor die, comprising:
during the ON state, driving base current into one of the base contact regions; and
during transition to the OFF state,
temporarily shorting the base contact region on the first surface to the emittercollector region on the first surface, while also shorting the base contact region on the second surface to the emittercollector region on the second surface, and thereafter
floating at least the base contact region on the first surface;
wherein the base contact region on the first surface is not connected to the base contact region on the second surface;
whereby currents of both polarities are controllably switched between the emittercollector regions on opposite surfaces.
93. The method of claim 92, wherein the semiconductor die is silicon.
94. The method of claim 92, further comprising the preliminary step, in the ON state, of conducting current as a diode, before the step of flowing base current.
95. A method for switching a power bipolar semiconductor device which includes both first-conductivity-type emittercollector regions and also second-conductivity-type base contact regions on both opposed surfaces of a semiconductor die, comprising the actions of:
beginning turn-off by temporarily connecting the base contact and emittercollector regions on the first surface together, while separately connecting the base contact and emittercollector regions on the second surface together, without connecting the base contact region on the first surface to the base contact region on the second surface; and then
floating one, but not both, of the base contact regions;
whereby the total time required for turn-off is reduced.
96. The method of claim 95, wherein the semiconductor die is silicon.
97. The method of claim 95, further comprising, during the ON state, applying base current to one of the base contact regions.
98. The method of claim 97, wherein said step of applying base current supplies base current to the base contact region.
99. The method of claim 97, wherein the step of applying base current draws current from the base contact region.
100. The method of claim 95, further comprising the preliminary step, in the ON state, of conducting current as a diode, before the step of flowing base current.
101. A method for switching a power bipolar semiconductor device which includes both a p-type emittercollector region, and also an n-type base contact region, on both first and second surfaces of an n-type semiconductor die, comprising:
during the ON state, driving one of the base contact regions toward a voltage lower than the nearest emittercollector region; and
during transition to the OFF state,
temporarily shorting the base contact region on the first surface to the emittercollector region on the first surface, while also shorting the base contact region on the second surface to the emittercollector region on the second surface, and thereafter
floating the base contact region on the first surface, but not the base contact region on the second surface;
whereby currents of both polarities are controllably switched between the emittercollector regions on opposite surfaces.
102. The method of claim 101, wherein the semiconductor die is silicon.
103. The method of claim 101, wherein said driving step draws current from the base contact region.
104. The method of claim 101, further comprising the preliminary step, in the ON state, of conducting current as a diode, before the step of flowing base current.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic system comprising:
a first power supply having a first voltage level;
a second power supply having a second voltage level lower than said first voltage level;
a first load connected to be powered by said first power supply;
a first voltage monitor circuit connected to said first power supply to be powered by said first power supply and to sense said first power supply, said first voltage monitor circuit generating a first output signal indicating whether said first voltage level of said first power supply is within predetermined limits;
a second voltage monitor circuit connected to said first power supply to be powered by said first power supply, connected to said second power supply to sense said second power supply, said second voltage monitor circuit generating a second output signal indicating whether said second voltage level of said second power supply is within predetermined limits;
a second load;
a power switch connected to said second power supply, said first voltage monitor circuit and said second load, said power switch having a closed state connecting said second power supply to said second load if said first output signal indicates said first voltage level of said first power supply is within said predetermined limits and having an open state isolating said second power supply from said second load if said first output signal indicates said first voltage level of said first power supply not is within said predetermined limits.
2. The electronic system of claim 1, wherein:
said first load includes input and output circuits.
3. The electronic system of claim 1, wherein:
said first load includes analog circuits.
4. The electronic system of claim 1, wherein:
said second load includes digital memory.
5. The electronic system of claim 1, wherein:
said second load includes digital logic circuits.
6. The electronic system of claim 5, wherein:
said first voltage circuit generating a reset signal if said first voltage level of said first power supply not is within predetermined limits; and
said digital logic circuits are connected to said first voltage monitor circuit to reset upon receiving said reset signal from said first voltage monitor circuit.