1. A method of manufacturing a semiconductor device comprising:
forming an n-type semiconductor region and a p-type semiconductor region on a semiconductor substrate;
forming a first gate dielectric layer above the n-type semiconductor region and the p-type semiconductor region;
forming a second gate dielectric layer above the p-type semiconductor region, the second gate dielectric layer being made of an insulating material different from that of a the first gate dielectric layer; and
forming a gate electrode layer on the first gate dielectric layer and the second gate dielectric layer, such that a relation:
(XB\u2212XA)\xd7(dA+dB)\u22673.9
is satisfied by electronegativity (XA) and an atomic radius (dA, a unit thereof is \u212b) of a metal element constituting the gate electrode layer and by electronegativity (XB) and an atomic radius (dB) of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the first gate dielectric layer facing the gate electrode layer.
2. The method according to claim 1, further comprising:
removing the first gate dielectric layer on the p-type semiconductor region, after said forming a first gate dielectric layer and before said forming a second gate dielectric layer.
3. The method according to claim 2, further comprising:
forming a first gate electrode above the n-type semiconductor region and a second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.
4. The method according to claim 3, further comprising:
forming an insulating layer over the n-type semiconductor region and the p-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and
flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.
5. The method according to claim 1, wherein said forming a second gate dielectric layer above the p-type semiconductor region includes forming the second gate dielectric layer above the p-type semiconductor region with the first gate dielectric layer interposed therebetween.
6. The method according to claim 5, further comprising:
forming the first gate electrode above the n-type semiconductor region and the second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.
7. The method according to claim 6, further comprising:
forming an insulating layer over the n-type semiconductor region and the p-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and
flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.
8. The method according to claim 5, wherein said forming a second gate dielectric layer above the p-type semiconductor region includes forming the second gate dielectric layer so as to have a thickness of one or more mono layers and 2 nm or less.
9. The method according to claim 1, wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(XC\u2212XA)\xd7(dA+dC)\u22660.7
is satisfied, wherein XC and dC (a unit thereof is \u212b) are electronegativity and an atomic radius of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the second dielectric above the p-type semiconductor region facing the gate electrode layer.
10. The method according to claim 9, wherein said forming a gate electrode layer includes forming the gate electrode layer using the metal element having the electronegativity of 1.78 or less.
11. The method according to claim 9, wherein said forming a gate electrode layer includes forming the gate electrode layer such that the gate electrode layer is made of a compound AmXn of a metal element A and another element X, and electronegativities XA and XX of the metal element A and the metal element X satisfy a relation:
\u03c7
A
m
\u2062
\u03c7
X
n
m
+
n
\u2264
1.78
12. A method of manufacturing a semiconductor device: comprising;
forming an n-type semiconductor region and a p-type semiconductor region (5) on a semiconductor substrate;
forming a first gate dielectric layer above the n-type semiconductor region and the p-type semiconductor region;
forming a second gate dielectric layer above the n-type semiconductor region, the second gate dielectric layer being made of an insulating material different from that of a the first gate dielectric layer; and
forming a gate electrode layer on the first gate dielectric layer and the second gate dielectric layer, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, such that a relation:
(XB\u2212XA)\xd7(dA+dB)\u22673.9
is satisfied by electronegativity (XA) and an atomic radius (dA, a unit thereof is \u212b) of a metal element constituting the gate electrode layer and by electronegativity (XB) and an atomic radius (dB) of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the second gate dielectric layer facing the gate electrode layer.
13. The method according to claim 12, wherein said forming a second gate dielectric layer above the n-type semiconductor region includes forming the second gate dielectric layer above the n-type semiconductor layer with the first gate dielectric layer interposed therebetween.
14. The method according to claim 13, further comprising:
forming the first gate electrode above the n-type semiconductor region and the second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.
15. The method according to claim 14, further comprising:
forming an insulating layer over the n-type semiconductor region and the p-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and
flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.
16. The method according to claim 13, wherein said forming a second gate dielectric layer above the n-type semiconductor region includes forming the second gate dielectric layer so as to have a thickness of one or more mono layers and 2 nm or less.
17. The method according to claim 12, wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(XC\u2212XA)\xd7(dA+dC)\u22660.7
is satisfied, wherein XC and dC (a unit thereof is \u212b) are electronegativity and an atomic radius of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the first dielectric above the p-type semiconductor region facing the gate electrode layer.
18. The method according to claim 12, wherein said forming a gate electrode layer includes forming the gate electrode layer using the metal element having the electronegativity of 1.78 or less.
19. The method according to claim 12, wherein said forming a gate electrode layer includes forming the gate electrode layer such that the gate electrode layer is made of a compound AmXn of a metal element A and another element X, and electronegativities XA and XX of the metal element A and the metal element X satisfy a relation:
\u03c7
A
m
\u2062
\u03c7
X
n
m
+
n
\u2264
1.78
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A composite material having utility in the manufacture of jewelry components, comprising:
a precious metal layer; and
a support layer formed from an age-hardenable non-precious metal-base alloy laminated to a first side of said precious metal layer.
2. The composite material of claim 1 wherein said precious metal layer is selected from the group consisting of gold, silver, platinum, 10 k and higher gold alloys, silver-base alloys containing at least 80%, by weight, silver and platinum-base alloys containing at least 50%, by weight, platinum.
3. The composite material of claim 2 wherein said precious metal layer is a 10 k or higher gold alloy.
4. The composite material of claim 2 wherein said support layer is an age-hardenable copper-base alloy.
5. The composite material of claim 4 wherein said support layer is a spinodal copper-base alloy.
6. The composite material of claim 5 wherein said support layer is a copper-base alloy containing from 3% to 30%, by weight, nickel and 2% -10%, by weight, tin.
7. The composite material of claim 6 wherein said support layer is a copper-base alloy containing from 6% to 10%, by weight, nickel and 3% to 7%, by weight, tin.
8. The composite material of claim 7 wherein said support layer is a copper-base alloy containing 7% to 8%, by weight, nickel and 4.5% to 5.5%, by weight, tin.
9. The composite material of claim 3 wherein said support layer is a copper-base alloy containing 7% to 8%, by weight, nickel and 4.5% to 5.5%, by weight, tin.
10. The composite material of claim 4 wherein a first solder layer is disposed between said precious metal layer and said support layer.
11. The composite material of claim 4 wherein said first solder layer is selected to lie a silver containing braze or solder.
12. The composite material of claim 10 wherein an intervening support layer and a second solder layer are disposed between said first solder layer and said support layer.
13. The composite material of claim 12 wherein said second solder layer is selected to be a silver containing braze or solder with a melting temperature less than the first solder layer.
14. The composite material of claim 4 further including a second precious metal layer bonded to an opposing second side of said support layer.
15. The composite material of claim 10 wherein a second precious metal layer is bonded to an opposing second side of said support layer by a third solder layer.
16. The composite material of claim 12 wherein a second precious metal layer is bonded to an opposing second side of said support layer by a third solder layer with an intervening support layer and a fourth solder layer interposed between said third solder layer and said support layer.
17. A method for the manufacture of a composite material having utility as a jewelry component, comprising the steps of:
a). bonding a precious metal layer to a first side an age hardenable non-precious metal support layer thereby forming said composite material; and
b). age hardening said composite material.
18. The method of claim 17 wherein said precious metal layer is selected from the group consisting of a gold alloy of 10 k or higher, a silver-base alloy containing at least 80% by weight of silver and platinum-base alloys containing at least 50% by weight platinum and said non-precious metal support layer is selected to be a copper-base spinodal alloy.
19. The method of claim 18 wherein prior to age-hardening said composite material, said composite material is annealed and formed into a desired shape.
20. The method of claim 19 wherein an annealing temperature is higher than an age hardening temperature.
21. The method of claim 20 wherein said annealing temperature is from 538 C. to 593 C. and said age hardening temperature is from 300 C. to 500 C.
22. A method for the manufacture of wire having utility in the manufacture of jewelry components, comprising the steps of:
a). forming a composite of a precious metal layer bonded to an intervening support layer;
b). forming said composite into a tubular configuration with a centrally disposed bore of diameter d, said intervening support layer forming sidewalls of said centrally disposed bore;
c). bonding a rod of age-hardenable material into said centrally disposed bore;
d). reducing the diameter to said composite and rod assembly to a desired diameter for said wire;
e). forming said wire into a desired jewelry component; and
f). age hardening said desired jewelry component.
23. The method of claim 22 wherein said precious metal layer is selected from the group consisting of a gold alloy of 10 k or higher, a silver-base alloy containing at least 80% by weight of silver and platinum-base alloys containing at least 50% by weight platinum and said non-precious metal support layer is selected to be a copper-base spinodal alloy.
24. The method of claim 23 wherein prior to age-hardening said composite material, said composite material is annealed and formed into a desired shape.
25. The method of claim 24 wherein an annealing temperature is higher than an age hardening temperature.
26. The method of claim 25 wherein said annealing temperature is from 538 C. to 593 C. and said age hardening temperature is from 300 C. to 500 C.
27. A method for the manufacture of wire having utility in the manufacture of jewelry components, comprising the steps of:
a). forming a precious metal cylinder having a central bore of diameter d;
b). bonding a rod of age-hardenable material into said central bore forming a composite;
c). reducing the diameter to said composite to a desired diameter for said wire;
d) forming said wire into a desired jewelry component; and
e). age hardening said desired jewelry component.
28. The method of claim 27 wherein said precious metal layer is selected from the group consisting of a gold alloy of 10 k or higher, a silver-base alloy containing at least 80% by weight of silver and platinum-base alloys containing at least 50% by weight platinum and said non-precious metal support layer is selected to be a copper-base spinodal alloy.
29. The method of claim 28 wherein prior to age-hardening said composite material, said composite material is annealed and formed into a desired shape.
30. The method of claim 29 wherein an annealing temperature is higher than an age. hardening temperature.
31. The method of claim 30 wherein said annealing temperature is from 538 C. to 593 C. and said age hardening temperature is from 300 C. to 500 C.