1. A method comprising:
heating an integrated circuit (IC) chip, disposed within an IC chip package, to an elevated temperature, said integrated circuit (IC) chip including a flash memory that includes blocks of flash memory cells, each of said flash memory cells including a control gate separated from a floating gate, which is separated from a channel region in a semiconductor substrate of a field effect transistor by a tunnel dielectric;
applying a negative electric field to each of said blocks of flash memory cells at said elevated temperature, said negative electric field causing a trapped negative charge in said tunnel dielectric to quantum tunnel to said channel region, effecting a field effect transistor threshold voltage shift of said flash memory cells;
terminating said applying of said negative electric field to each of said blocks of flash memory cells and then terminating said heating of said integrated circuit (IC) chip;
allowing said integrated circuit (IC) chip to return to an ambient temperature; and
retrieving data for each of said blocks of flash memory cells from a storage device and rewriting said data into each of said blocks of flash memory cells.
2. The method of claim 1, said heating of said integrated circuit (IC) chip being caused by Joule heating of a resistive element disposed in any of: a chip carrier of said IC chip package that thermally contacts said integrated circuit (IC) chip; an attachment to said chip carrier of said IC chip package that thermally contacts said integrated circuit (IC) chip; an area of said integrated circuit (IC) chip that is devoid of said flash memory; a cover that thermally contacts said integrated circuit (IC) chip of said IC chip package; and an attachment to said cover that thermally contacts said integrated circuit (IC) chip of said IC chip package.
3. The method of claim 1, said elevated temperature being less than or equal to 250\xb0 C.
4. The method of claim 1, said negative electric field being generated by one of: a voltage between said control gate and said semiconductor substrate of said field effect transistor of each of said flash memory cells; a voltage between said control gate and a metal layer of said field effect transistor of each of said flash memory cells; a voltage between a plurality of metal layers where said field effect transistor lies between said plurality of metal layers of said flash memory cells; a voltage between electrodes attached to one of said IC chip package and said integrated circuit (IC) chip; and a voltage between electrodes embedded in one of said IC chip package and said integrated circuit (IC) chip.
5. The method of claim 1, further comprising copying data from each of said block of flash memory cells to said storage device prior to heating said integrated circuit (IC) chip.
6. The method of claim 1, said applying of said negative electric field to each of said blocks of flash memory cells at said elevated temperature occurring sequentially over individual blocks of flash memory for an address space that addresses all functional blocks of said flash memory.
7. The method of claim 1, said applying of said negative electric field to each of said blocks of flash memory cells at said elevated temperature occurring simultaneously over an address space that addresses all functional blocks of said flash memory.
8. A method comprising:
copying data from blocks of flash memory cells comprising a flash memory disposed within an integrated circuit (IC) chip, which is disposed within an IC chip package, to a storage device, each of said flash memory cells including a control gate separated from a floating gate, which is separated from a channel region in a semiconductor substrate of a field effect transistor by a tunnel dielectric;
heating said integrated circuit (IC) chip to an elevated temperature;
applying a negative electric field to each of said blocks of flash memory cells sequentially over individual blocks of said flash memory for an address space that addresses all functional blocks of said flash memory at said elevated temperature, said negative electric field causing a trapped negative charge in said tunnel dielectric to quantum tunnel to said channel region, effecting a field effect transistor threshold voltage shift of said flash memory cells;
terminating said applying of said negative electric field to each of said blocks of flash memory cells and then terminating said heating of said integrated circuit (IC) chip;
allowing said integrated circuit (IC) chip to return to an ambient temperature; and
retrieving data for each of said blocks of flash memory cells from said storage device and rewriting said data into each of said blocks of flash memory cells.
9. The method of claim 8, said heating of said integrated circuit (IC) chip being caused by Joule heating of a resistive element disposed in any of: a chip carrier of said IC chip package that thermally contacts said integrated circuit (IC) chip; an attachment to said chip carrier of said IC chip package that thermally contacts said integrated circuit (IC) chip; an area of said integrated circuit (IC) chip that is devoid of said flash memory; a cover that thermally contacts said integrated circuit (IC) chip of said IC chip package; and an attachment to said cover that thermally contacts said integrated circuit (IC) chip of said IC chip package.
10. The method of claim 8, said elevated temperature being less than or equal to 250\xb0 C.
11. The method of claim 8, said negative electric field being generated by one of: a voltage between said control gate and said semiconductor substrate of said field effect transistor of each of said flash memory cells; a voltage between said control gate and a metal layer of said field effect transistor of each of said flash memory cells; a voltage between a plurality of metal layers where said field effect transistor lies between said plurality of metal layers of said flash memory cells; a voltage between electrodes attached to one of said IC chip package and said integrated circuit (IC) chip; and a voltage between electrodes embedded in one of said IC chip package and said integrated circuit (IC) chip.
12. The method of claim 8, said negative electric field being provided by a voltage ranging from \u22125V to \u221220V.
13. The method of claim 8, said applying of said negative electric field to each of said blocks of flash memory cells at said elevated temperature sequentially over individual blocks of said flash memory occurring cyclically over multiple cycles for a selectable duration.
14. A method comprising:
copying data from blocks of flash memory cells comprising a flash memory disposed within an integrated circuit (IC) chip, which is disposed within an IC chip package, to a storage device, each of said flash memory cells including a control gate separated from a floating gate, which is separated from a channel region in a semiconductor substrate of a field effect transistor by a tunnel dielectric;
heating said integrated circuit (IC) chip to an elevated temperature;
applying a negative electric field to each of said blocks of flash memory cells simultaneously over individual blocks of said flash memory for an address space that addresses all functional blocks of said flash memory at said elevated temperature, said negative electric field causing a trapped negative charge in said tunnel dielectric to quantum tunnel to said channel region, effecting a field effect transistor threshold voltage shift of said flash memory cells;
terminating said applying of said negative electric field to each of said blocks of flash memory cells and then terminating said heating of said integrated circuit (IC) chip;
allowing said integrated circuit (IC) chip to return to an ambient temperature; and
retrieving data for each of said blocks of flash memory cells from said storage device and rewriting said data into each of said blocks of flash memory cells.
15. The method of claim 14, said heating of said integrated circuit (IC) chip being caused by Joule heating of a resistive element disposed in any of: a chip carrier of said IC chip package that thermally contacts said integrated circuit (IC) chip; an attachment to said chip carrier of said IC chip package that thermally contacts said integrated circuit (IC) chip; an area of said integrated circuit (IC) chip that is devoid of said flash memory; a cover that thermally contacts said integrated circuit (IC) chip of said IC chip package; and an attachment to said cover that thermally contacts said integrated circuit (IC) chip of said IC chip package.
16. The method of claim 14, said elevated temperature being less than or equal to 250\xb0 C.
17. The method of claim 14, said negative electric field being generated by one of: a voltage between said control gate and said semiconductor substrate of said field effect transistor of each of said flash memory cells; a voltage between said control gate and a metal layer of said field effect transistor of each of said flash memory cells; a voltage between a plurality of metal layers where said field effect transistor lies between said plurality of metal layers of said flash memory cells; a voltage between electrodes attached to one of said IC chip package and said integrated circuit (IC) chip; and a voltage between electrodes embedded in one of said IC chip package and said integrated circuit (IC) chip.
18. The method of claim 14, said negative electric field ranging from \u22125V to \u221220V.
19. The method of claim 14, said applying of said negative electric field to each of said blocks of flash memory cells at said elevated temperature simultaneously over individual blocks of said flash memory occurring cyclically over multiple cycles for a selectable duration.
20. The method of claim 14 further comprising reading and verifying said data that is rewritten into each of said blocks of flash memory cells.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-7. (canceled)
8. A method for joining at least one joint part, comprising the steps of:
inserting a hollow profile into a through-opening of a joint part up to a joint point;
providing an adhesive between an inner side of the joint part and an outer side of the hollow profile at the joint point;
expanding the hollow profile at least at the joint point,
wherein
the adhesive is provided in an annular recess formed on at least one of the inner side of the joint part and on the outer side of the hollow profile, and
the recess is configured such that during the expansion step the recess is essentially leveled and the adhesive is displaced over an area of the joint point.
9. The method as claimed in claim 8, wherein
the adhesive is fully encloses a circumference of the hollow profile.
10. The method as claimed in claim 8, wherein
the adhesive is provided between the joint part and the hollow profile before the hollow profile is inserted into the joint part, and
the adhesive is in a solid form when provided between the hollow profile and the joint part.
11. The method as claimed in claim 8, wherein
the hollow profile is also expanded directly adjacent to the joint part such that after expansion, at least on one side of the joint part a step bears laterally against the joint part.
12. The method as claimed in claims 8 wherein
the hollow profile is expanded by application of internal high pressure.
13. A hollow profile joint, comprising:
a hollow profile;
a joint part; and
an adhesive.
wherein
the hollow profile is located in a through-opening of the joint part at a joint point, and is expanded at least at the joint point and adjacent to the joint part such that an annular bead-shaped step formed on the hollow profile bears against the joint part, and
the adhesive is located between an inner side of the joint part and an outer side of the hollow profile at the joint point.
14. The hollow profile as claimed in claim 13, wherein the joint part has a fastening section arranged to permit fastening of the combined joint part and hollow profile to another component.