1. A method of fitting a cochlear implant, the cochlear implant having an electrode array with multiple electrode contacts through which a pulsatile stimulation waveform having a pulse rate and a pulse width may be applied to the cochlea of the patient; and wherein the fitting method builds an M iso-loudness contour and determines a T iso-loudness contour, the method comprising:
a) setting a starting sound level to build an iso-loudness contour;
b) setting volume on a first channel until the sound is at a predetermined level;
c) adjusting volume on a second channel until the volume of sound on the second channel is similar to the volume of sound on the first channel; then
d) setting the next channel to result in the same sound volume determined for the previous channel;
e) repeating step (d) for each available channel until the stimulation level for the last channel is adjusted, and the M iso-loudness contour is built; and
f) picking one channel and determining the volume level of that one channel; and
g) generating a T-iso-loudness contour by determining the difference in the volume level measured for the one channel in step f) and the M volume level found previously for that channel and linearly shifting the M iso-loudness contour by the determined difference in volume level.
2. The method of claim 1 wherein the starting sound level is no sound.
3. The method of claim 1 wherein the sound includes a tone or tones.
4. The method of claim 1 wherein the sound includes noise.
5. The method of claim 1 wherein the sound includes speech.
6. The method of claim 1 wherein the predetermined level is a comfortable level.
7. The method of claim 1 wherein the predetermined level is a threshold level.
8. The method of claim 1 wherein at least one channel is a virtual channel.
9. The method of claim 1 wherein at least one channel is skipped.
10. A method of fitting a cochlear implant, the cochlear implant having an electrode array with multiple electrode contacts through which a pulsatile stimulation waveform having a pulse rate and a pulse width may be applied to the cochlea of the patient; and wherein the fitting method sets an iso-loudness contour from an iso-neural response contour, the method comprising:
determining an iso-neural response contour; and
linearly transposing the iso-neural contour to set an iso-loudness contour.
11. The method of claim 10 further comprising using at least one of neural response imaging and evoked auditory brainstem response to determine the iso-neural response contour.
12. The method of claim 10 further comprising
determining an M level for at least one channel;
determining a difference between the iso-neural level and the M level for the at least one channel; and
linearly transposing the iso-neural contour by the amount of the difference to set the iso-loudness contour.
13. The method of claim 10 wherein the iso-loudness contour is an M iso-loudness contour.
14. The method of claim 10 wherein the iso-loudness contour is a T iso-loudness contour.
15. A method of fitting a cochlear implant, the cochlear implant having an electrode array with multiple electrode contacts through which a pulsatile stimulation waveform having a pulse rate and a pulse width may be applied to the cochlea of the patient; and wherein the fitting method uses at least two iso-loudness contours, the method comprising:
determining a first iso-loudness response contour; and
linearly transposing the first iso-loudness contour to set a second iso-loudness contour.
16. The method of claim 15 wherein the first iso-loudness contour is an M iso-loudness contour.
17. The method of claim 16 wherein the second iso-loudness contour is a T iso-loudness contour.
18. The method of claim 15 further comprising:
determining a difference between the first iso-loudness contour level and the second iso-loudness contour using at least one channel; and
linearly transposing the first iso-loudness contour by the amount of the difference to set the second iso-loudness contour.
19. A method of fitting a cochlear implant, the cochlear implant having an electrode array with multiple electrode contacts through which a pulsatile stimulation waveform having a pulse rate and a pulse width may be applied to the cochlea of the patient; and wherein the fitting method determines an iso-loudness contour, the method comprising:
setting pulse width to about 30 \u03bcs to about 75 \u03bcs;
determining an iso-loudness contour with the set pulse width; and
linearly transposing the iso-loudness contour for use with pulse widths of about 10 \u03bcs to about 20 \u03bcs.
20. The method of claim 19 further comprising:
determining a difference between the iso-loudness contour level with the set pulse width and a comfortable volume for pulse widths of about 10 \u03bcs to about 20 \u03bcs; and
linearly transposing the iso-loudness contour by the amount of the difference.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A micromechanical structure comprising:
a silicon (Si) based substrate;
a micromechanical element formed directly on the substrate; and
an undercut formed underneath a released portion of the micromechanical element;
wherein the undercut is in the form of a recess formed in the Si based substrate.
2. The structure as claimed in claim 1, wherein the Si based substrate comprises a silicon-on-insulator (SOI) substrate.
3. The structure as claimed in claim 2, wherein a thickness of a Si overlayer of the SOI substrate is chosen for controlling a stress in the released portion of the micromechanical element.
4. The structure as claimed in claim 2 or 3, wherein the recess extends through substantially the thickness of the Si overlayer of the SOI substrate.
5. The structure as claimed in any one of claims 3 to 4, wherein the thickness is in a range of about 10 nm to about 10 \u03bcm.
6. The structure as claimed in any one of claims 2 to 5, wherein the SOI substrate is provided using wafer bonding, Separation by Implantation of Oxygen (SIMOX) or both.
7. The structure as claimed in any one of claims 2 to 6, wherein a crystalline orientation of the SOI substrate is chosen for controlling the stress in the released portion of the micromechanical element.
8. The structure as claimed in claim 7, wherein the crystalline orientation is (100) or (111).
9. The structure as claimed in claim 1, wherein the Si based substrate comprises a bulk Si substrate.
10. The structure as claimed in claim 9, wherein the bulk Si substrate comprises a crystalline orientation of (100) or (111).
11. The structure as claimed in any of the preceding claims, wherein the micromechanical element comprises one or more materials selected from a group consisting ZnO, Zn(Mg)O, Zn(Cd)O, ZnS, GaN, AlN, AlGaN, InGaN, InN, polycrystalline diamond and nanocrystalline diamond.
12. The structure as claimed in any of the preceding claims, wherein the recess is formed in the Si based substrate using a dry etch process.
13. The structure as claimed in claim 12, wherein the dry etch process comprises usage of XeF2.
14. The structure as claimed in any of the preceding claims, wherein the micromechanical element comprises an optoelectronic device.
15. The structure as claimed in any of the preceding claims, wherein the micromechanical element comprises a microelectronic device.
16. The structure as claimed in claim 14, wherein the optoelectronic device comprises a light emitting diode (LED).
17. The structure as claimed in claim 15, wherein the microelectronic device comprises one or more Field-effect transistors (FETs).
18. A method of fabricating a micromechanical structure, the method comprising the steps of:
providing a silicon (Si) based substrate;
forming a micromechanical element directly on the substrate;
forming an undercut in the form of a recess underneath a released portion of the micromechanical element; and
forming the recess in the Si based substrate.
19. The method as claimed in claim 18, wherein the Si based substrate comprises a silicon-on-insulator (SOI) substrate.
20. The method as claimed in claim 19, further comprising choosing a thickness of a Si overlayer of the SOI substrate for controlling a stress in the released portion of the micromechanical element.
21. The method as claimed in claim 19 or 20, wherein the recess extends through substantially the thickness of the Si overlayer of the SOI substrate.
22. The method as claimed in any one of claims 20 to 21, wherein the thickness is in a range of about 10 nm to about 10 \u03bcm.
23. The method as claimed in any one of claims 19 to 22, wherein the Si based substrate is provided using wafer bonding, Separation by Implantation of Oxygen (SIMOX) or both.
24. The method as claimed in any one of claims 19 to 23, further comprising choosing a crystalline orientation of the SOI substrate for controlling the stress in the released portion of the micromechanical element.
25. The method as claimed in claim 24, wherein the crystalline orientation is (100) or (111).
26. The method as claimed in claim 18, wherein the Si based substrate comprises a bulk Si substrate.
27. The method as claimed in claim 26, wherein the bulk Si substrate comprises a crystalline orientation of (100) or (111).
28. The method as claimed in any one of claims 18 to 27, wherein the micromechanical element comprises one or more materials selected from a group consisting ZnO, Zn(Mg)O, Zn(Cd)O, ZnS, GaN, AlN, AlGaN, InGaN, InN polycrystalline diamond and nanocrystalline diamond.
29. The method as claimed in any one of claims 18 to 28, wherein the forming an undercut in the form of a recess comprises using a dry etch process.
30. The method as claimed in claim 29, wherein the dry etch process comprises using XeF2.
31. The method as claimed in any one of claims 18 to 30, wherein the micromechanical element comprises an optoelectronic device.
32. The method as claimed in any one of claims 18 to 31, wherein the micromechanical element comprises a microelectronic device.
33. The method as claimed in claim 31, wherein the optoelectronic device comprises a light emitting diode (LED).
34. The method as claimed in claim 32, wherein the microelectronic device comprises one or more Field-effect transistors (FETs).