1. A method for efficient discontinuous reception (\u2018DRX\u2019) operation during handover in Long Term Evolution (\u2018LTE\u2019) in which a user equipment expects handover to occur between a source enhanced Node B (\u2018eNB\u2019) and a target eNB, the method comprising the steps of:
checking whether a message indicating handover initiation will not occur is received at the user equipment from the source eNB within a predetermined time period;
if no, performing the steps of: ensuring the user equipment is not in a DRX sleep period during reception of a handover grant;
checking whether a handover grant is received, and if yes, performing a handover procedure; and if no, resuming a DRX sleep interval; and
if yes, ending the process.
2. The method of claim 1, wherein the step of ensuring the user equipment is not in the DRX sleep period utilizes continuous reception on the user equipment.
3. The method of claim 1, wherein the step of ensuring the user equipment is not in the DRX sleep period utilizes an extended DRX awake period.
4. The method of claim 1, wherein
the step of ensuring the user equipment is not in the DRX sleep period utilizes a short DRX period;
the short DRX period has a length set based on a value that is one of received from the source eNB or pre-configured; and,
the value is predetermined and stored on the source eNB.
5-7. (canceled)
8. The method of claim 1, wherein checking whether the message is received further comprises:
making, at the source eNB, the handover initiation decision; and
signaling the handover initiation decision to the user equipment.
9. The method of claim 1 further comprising, after said resuming step, receiving updated measurement control information for handover procedures.
10. The method of claim 1, wherein the user equipment is expecting handover to occur based on the sending of a measurement report.
11. The method of claim 1, wherein the user equipment is expecting handover to occur based on a parameter in the measurement report being above or below a predetermined threshold.
12. A system for efficient discontinuous reception (\u2018DRX\u2019) operation during handover in Long Term Evolution (\u2018LTE\u2019) comprising user equipment and an enhanced node B, the system configured to:
check by the user equipment whether a message indicating handover initiation will not occur is received within a predetermined time period;
if no:
ensure the user equipment is not in a DRX sleep period during reception of a handover grant;
check whether a handover grant is received, and
if yes, perform a handover procedure; and
if no, resume a DRX sleep interval.
13. The system of claim 12, wherein ensuring that the user equipment is not in the DRX sleep period comprises utilizing continuous reception on the user equipment.
14. The system of claim 12, wherein the ensuring that the user equipment is not in the DRX sleep period comprises utilizing an extended DRX awake period.
15. The system of claim 12, wherein
the ensuring that the user equipment is not in the DRX sleep period comprises utilizing a short DRX period;
the short DRX period has a length set based on a value that is one of received from an enhanced node B or pre-configured; and,
the value is predetermined and stored on the enhanced node B.
16-18. (canceled)
19. The system of claim 12 wherein the system is further configured to receive, at the user equipment, updated measurement control information for handover procedure.
20. The system of claim 12, wherein the user equipment is configured to expect handover to occur based on the sending of a measurement report.
21. The method of claim 12, wherein the user equipment is configured to expect handover to occur based on a parameter in the measurement report being above or below a predetermined threshold.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer-implemented method for verifying a RAIMECC design using a hierarchical error injection scheme, the method comprising:
selecting marks for generating an error mask, the marks corresponding to at least one of: a marked channel and at least one marked chip;
selecting a fixed bit flip mask based on the selected marks;
determining that errors should be injected into the at least one of the marked channel and the at least one marked chip;
randomly injecting, by a computer, errors into the at least one of the marked channel and the at least one marked chip based on the determining that the errors should be injected into the at least one of the marked channel and the at least one marked chip, the injecting based on at least one of the fixed bit flip mask and a random bit flip mask;
determining that errors should be injected into an unmarked chip; and
based on the determining that errors should be injected into an unmarked chip:
selecting an unmarked channel;
selecting an unmarked chip from the unmarked channel; and
selecting the random bit flip mask or the fixed bit flip mask for the selected unmarked chip.
2. The computer-implemented method of claim 1, further comprising:
determining whether to inject a special uncorrectable error based determining that errors should be injected into the at least one of the marked channel and the at least one marked chip.
3. The computer-implemented method of claim 1, wherein the randomly injecting errors into the marked channel comprises:
selecting a chip mask to control which chips within the marked channel are to be injected with errors; and
selecting the random bit flip mask or the fixed bit flip mask for each chip within the marked channel to be injected with errors.
4. The computer-implemented method of claim 1, wherein the randomly injecting errors into the at least one marked chip comprises:
selecting the random bit flip mask or the fixed bit flip mask for the at least one marked chip.
5. The computer-implemented method of claim 1, further comprising:
determining whether to inject errors into multiple unmarked chips on different channels;
and
determining whether to inject errors into multiple unmarked chips from a same channel.
6. The computer-implemented method of claim 5, wherein based on determining to inject errors into multiple unmarked chips on different channels, the method further comprises:
selecting at least two unmarked channels;
selecting one unmarked chip from each of the at least two unmarked channels selected; and
selecting the random bit flip mask or the fixed bit flip mask for the selected unmarked chips.
7. The computer-implemented method of claim 5, wherein based on determining to inject errors into multiple chips from a same channel, the method further comprises:
selecting one unmarked channel;
selecting at least two unmarked chips from the unmarked channel; and
selecting the random bit flip mask or the fixed bit flip mask for each of the at least two unmarked chips.
8. A computer-program product for verifying a RAIMECC design using a hierarchical error injection scheme, the computer program product comprising:
a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
selecting marks for generating an error mask, the marks corresponding to at least one of: a marked channel and at least one marked chip;
selecting a fixed flip bit mask based on the selected marks;
determining that errors should be injected into the at least one of the marked channel and the at least one marked chip; and
randomly injecting errors into the at least one of the marked channel and the at least one marked chip based on the determining that the errors should be injected into the at least one of the marked channel and the at least one marked chip, the injecting based on at least one of the fixed bit flip mask and a random bit flip mask;
determining that errors should be injected into an unmarked chip; and
based on the determining that errors should be injected into an unmarked chip:
selecting an unmarked channel;
selecting an unmarked chip from the unmarked channel; and
selecting the random bit flip mask or the fixed bit flip mask for the selected unmarked chip.
9. The computer-program product of claim 8, wherein the method further comprises:
determining whether to inject a special uncorrectable error based upon determining that errors should be injected into the at least one of the marked channel and the at least one marked chip.
10. The computer-program product of claim 8, wherein the randomly injecting errors into the marked channel comprises:
selecting a chip mask to control which chips within the marked channel are to be injected with errors; and
selecting the random bit flip mask or the fixed bit flip mask for each chip within the marked channel to be injected with errors.
11. The computer-program product of claim 8, wherein the randomly injecting errors into the at least one marked chip comprises:
selecting the random bit flip mask or the fixed bit flip mask for the at least one marked chip.
12. The computer-program product of claim 8, wherein the method further comprises:
determining whether to inject errors into multiple unmarked chips on different channels;
and
determining whether to inject errors into multiple unmarked chips from a same channel.
13. The computer-program product of claim 12, wherein based on determining to inject errors into multiple unmarked chips on different channels, the method further comprises:
selecting at least two unmarked channels;
selecting one unmarked chip from each of the at least two unmarked channels selected; and
selecting the random bit flip mask or the fixed bit flip mask for the selected unmarked chips.
14. The computer-program product of claim 12, wherein based on determining to inject errors into multiple chips from the same channel, the method further comprises:
selecting one unmarked channel;
selecting at least two unmarked chips from the unmarked channel; and
selecting the random bit flip mask or the fixed bit flip mask for each of the at least two unmarked chips.
15. A system for verifying a RAIMECC design using a hierarchical error injection scheme, the system comprising:
a processor coupled with a controller;
the system configured to perform a method, the method comprising:
selecting marks for generating an error mask, the marks corresponding to at least on of: a marked channel and at least one marked chip;
selecting a fixed bit flip mask based on the selected marks;
determining that errors should be injected into the at least one of the marked channel and the at least one marked chip
randomly injecting errors into the at least one of the marked channel and the at least one marked chip based on the determining that the errors should be injected into the at least one of the marked channel and the at least one marked chip, the injecting based on at least one of the fixed bit flip mask and a random bit flip mask;
determining that errors should be injected into an unmarked chip; and
based on the determining that errors should be injected into an unmarked chip:
selecting an unmarked channel;
selecting an unmarked chip from the unmarked channel; and
selecting the random bit flip mask or the fixed bit flip mask for the selected unmarked chip.
16. The system of claim 15, wherein the method further comprises:
determining whether to inject a special uncorrectable error based on determining that errors should be injected into the at least one of the marked channel and the at least one marked chip.
17. The system of claim 15, wherein the randomly injecting errors into the marked channel comprises:
selecting a chip mask to control which chips within the marked channel are to be injected with errors; and
selecting the random bit flip mask or the fixed bit flip mask for each chip within the marked channel to be injected with errors.
18. The system of claim 15, wherein the randomly injecting errors into the at least one marked chip comprises:
select the random bit flip mask or the fixed bit flip mask for the at least one marked chip.
19. The system of claim 15, wherein the method further comprises:
determining whether to inject errors into multiple unmarked chips on different channels;
and
determining whether to inject errors into multiple unmarked chips from a same channel.
20. The system of claim 19, wherein based on determining to inject errors into multiple unmarked chips on different channels, the method further comprises:
selecting at least two unmarked channels;
selecting one unmarked chip from each of the at least two unmarked channels selected; and
selecting the random bit flip mask or the fixed bit flip mask for the selected unmarked chips.
21. The system of claim 19, wherein based on determining to inject errors into multiple chips from a same channel, the method further comprises:
selecting one unmarked channel;
selecting at least two unmarked chips from the unmarked channel; and
selecting the random bit flip mask or the fixed bit flip mask for each of the at least two unmarked chips.