1. A parallel successive-approximation analog-to-digital converter for generating a digital output signal based on an analog input signal, comprising:
a reference-voltage generation unit having a plurality of output terminals, wherein the reference-voltage generation unit is arranged to generate a unique reference-voltage on each of its output terminals, and each reference voltage and corresponding output terminal correspond to a unique digital number in a range Xmin, Xmax;
a plurality of sub analog-to-digital converters arranged for successive-approximation operation in a time-interleaved manner;
a reference-voltage selection unit operatively connected to the reference-voltage generation unit for selecting a reference voltage generated by the reference-voltage generation unit based on a digital number XSA stored in a successive-approximation register of the parallel successive-approximation analog-to-digital converter and forwarding the selected reference voltage to a comparator arrangement of a respective sub analog-to-digital converter;
wherein the reference-voltage selection unit has a first and a second output terminal operatively connected to the comparator arrangement of the respective sub analog-to-digital converter and includes a first switch layer comprising a plurality of switch groups, wherein each switch group comprises a plurality of switch devices, each switch device in a switch group being operatively connected to a unique one of the output terminals of the reference-voltage generation unit by a first terminal of the switch device and to a common node of the switch group by a second terminal of the switch device, and, for each X in the range Xmin, Xmax, the switch devices connected to the output terminals of the reference voltage generation unit that correspond to X and Xmax+Xmin\u2212X belong to different switch groups; and
a second switch layer comprising, for each switch group in the first switch layer, a switch device operatively connected between the common node of the switch group and the first output terminal of the reference-voltage selection unit and a switch device operatively connected between the common node of the switch group and the second output terminal of the reference-voltage selection unit; and
wherein the parallel successive-approximation analog-to-digital converter comprises a control unit arranged to generate control signals for the switch devices in the reference-voltage selection unit based on the digital number XSA in the successive-approximation register for closing
a first selected switch device in the first switch layer that is connected to the output terminal of the reference-voltage generation unit that corresponds to XSA;
the switch device in the second switch layer that is connected between the common node of the switch group to which the first selected switch device belongs and the first output terminal;
a second selected switch device in the first switch layer that is connected to the output terminal of the reference-voltage generation unit that corresponds to Xmax+Xmin\u2212XSA; and
the switch device in the second switch layer that is connected between the common node of the switch group to which the second selected switch device belongs and the second output terminal; and
wherein the control unit includes
a first encoder to receive the digital number Xsa and output a first control signal to close both the first selected switch device in the first switch layer that is connected to the output terminal of the reference-voltage generation unit that corresponds to Xsa and the second selected switch device in the first switch layer in the first switch layer that is connected to the output terminal of the reference-voltage generation unit that corresponds to Xmax+Xmin\u2212Xsa; and
a second encoder to receive most significant bits of the digital number Xsa and output a second control signal to close both the switch device in the second switch layer that is connected between the common node of the switch group to which the first selected switch device belongs and the first output terminal and the switch device in the second switch layer that is connected between the common node of the switch group to which the second selected switch device belongs and the second output terminal.
2. The parallel successive-approximation analog-to-digital converter according to claim 1, wherein the number of switch groups in the first switch layer of each reference-voltage selection unit is an integer power of two.
3. The parallel successive-approximation analog-to-digital converter according to claim 2, wherein the number of switch groups in the first switch layer of each reference-voltage selection unit is at least four.
4. The parallel successive-approximation analog-to-digital converter according to claim 3, wherein the reference-voltage selection unit comprises one or more intermediate switch layers of switch devices operatively connected between the first switch layer and the second switch layer for selectably connecting switch devices in the first switch layer to the corresponding common node.
5. The parallel successive-approximation analog-to-digital converter according to claim 4, wherein each switch device in an intermediate switch layer of the one or more intermediate switch layers is connected by an input terminal of the switch device to between two and four switch devices in a preceding switch layer.
6. The parallel successive-approximation analog-to-digital converter according to claim 5, wherein each switch device in said intermediate switch layer is connected by an input terminal of the switch device to four switch devices in said preceding switch layer.
7. The parallel successive-approximation analog-to-digital converter according to claim 5, wherein each switch device in each intermediate switch layer is connected by an input terminal of the switch device to between two and four switch devices in a preceding switch layer.
8. The parallel successive-approximation analog-to-digital converter according to claim 7, wherein each switch device in each intermediate switch layer is connected by an input terminal of the switch device to four switch devices in said preceding switch layer.
9. The parallel successive-approximation analog-to-digital converter according to claim 8, wherein the reference-voltage generation unit comprises a resistor string.
10. A parallel successive-approximation analog-to-digital converter for generating a digital output signal based on an analog input signal, comprising:
a reference-voltage generation unit having a plurality of output terminals, wherein the reference-voltage generation unit is arranged to generate a unique reference-voltage on each of its output terminals, and each reference voltage and corresponding output terminal correspond to a unique digital number in a range Xmin, Xmax;
a plurality of sub analog-to-digital converters arranged for successive-approximation operation in a time-interleaved manner;
a reference-voltage selection unit operatively connected to the reference-voltage generation unit for selecting a reference voltage generated by the reference-voltage generation unit based on a digital number XSA stored in a successive-approximation register of the parallel successive-approximation analog-to-digital converter and forwarding the selected reference voltage to a comparator arrangement of a respective sub analog-to-digital converter;
wherein the reference-voltage selection unit has a first and a second output terminal operatively connected to the comparator arrangement of the respective sub analog-to-digital converter and includes a first switch layer comprising a plurality of switch groups, wherein each switch group comprises a plurality of switch devices, each switch device in a switch group being operatively connected to a unique one of the output terminals of the reference-voltage generation unit by a first terminal of the switch device and to a common node of the switch group by a second terminal of the switch device, and, for each X in the range Xmin, Xmax, the switch devices connected to the output terminals of the reference voltage generation unit that correspond to X and Xmax+Xmin\u2212X belong to different switch groups; and
a second switch layer comprising, for each switch group in the first switch layer, a switch device operatively connected between the common node of the switch group and the first output terminal of the reference-voltage selection unit and a switch device operatively connected between the common node of the switch group and the second output terminal of the reference-voltage selection unit; and
wherein parallel successive-approximation analog-to-digital converter comprises a control unit arranged to generate control signals for the switch devices in the reference-voltage selection unit based on the digital number XSA in the successive-approximation register for closing
a first selected switch device in the first switch layer that is connected to the output terminal of the reference-voltage generation unit that corresponds to XSA;
the switch device in the second switch layer that is connected between the common node of the switch group to which the first selected switch device belongs and the first output terminal;
a second selected switch device in the first switch layer that is connected to the output terminal of the reference-voltage generation unit that corresponds to Xmax+Xmin\u2212XSA; and
the switch device in the second switch layer that is connected between the common node of the switch group to which the second selected switch device belongs and the second output terminal;
wherein the successive-approximation register comprises N bits, the reference-voltage generation unit is a coarse reference-voltage generation unit arranged to generate reference voltages for determining K most significant bits of the digital output signal, the reference voltage selection unit is a coarse reference voltage selection unit arranged to select and forward reference voltages for determining the K most significant bits of the digital output signal, the digital number XSA is determined by the K most significant bits of the successive-approximation register, and the parallel successive-approximation analog-to-digital converter further comprises a fine reference-voltage generation unit for determining the N-K least significant bits of the digital output signal and a fine reference-voltage selection unit for determining the N-K least significant bits of the digital output signal; and, wherein the fine reference-voltage generation unit has a plurality of output terminals, wherein the fine reference-voltage generation unit is arranged to generate a unique reference voltage on each of its output terminals, and each reference voltage and corresponding output terminal correspond to a unique digital number in the range Xmin,LSB, Xmax,LSB and wherein
the fine reference-voltage selection unit has a first and a second output terminal operatively connected to the comparator arrangement of the respective sub analog-to-digital converter and comprises:
a third switch layer comprising a plurality of switch groups, wherein each switch group comprises a plurality of switch devices, each switch device in a switch group is operatively connected to a unique one of the output terminals of the fine reference-voltage generation unit by a first terminal of the switch device and to a common node of the switch group by a second terminal of the switch device, and, for each X in the range Xmin,LSB, Xmax,LSB, the switch devices connected to the output terminals of the fine reference-voltage unit that correspond to X and Xmin,LSB, Xmax,LSB-X belong to different switch groups;
a fourth switch layer comprising, for each switch group in the third switch layer, a switch device operatively connected between the common node of the switch group and the first output terminal of the fine reference-voltage selection unit and a switch device operatively connected between the common node of the switch group and the second output terminal of the fine reference-voltage selection unit; and
the parallel successive approximation analog-to-digital converter comprises a further control unit arranged to generate control signals for the switch devices in the fine reference-voltage selection unit of the respective sub analog-to-digital converter based on a digital number XSA,LSB determined by the N-K least significant bits of the successive-approximation register for closing
a third selected switch device in the third switch layer that is connected to the output terminal of the fine reference-voltage generation unit that corresponds to XSA,LSB;
the switch device in the fourth switch layer that is connected between the common node of the switch group to which the third selected switch device belongs and the first output terminal of the fine reference-voltage selection unit;
a fourth selected switch device in the third switch layer that is connected to the output terminal of the fine reference-voltage generation unit that corresponds to Xmax,LSB+Xmin,LSB-XSA,LSB;
and the switch device in the fourth switch layer that is connected between the common node of the switch group to which the fourth selected switch device belongs and the second output terminal of the fine reference-voltage selection unit.
11. The parallel successive-approximation analog-to-digital converter according to claim 10, wherein the number of switch groups in the third switch layer of each fine reference-voltage selection unit is an integer power of two.
12. The parallel successive-approximation analog-to-digital converter according to claim 11, wherein the number of switch groups in the third switch layer of each fine reference-voltage selection unit is at least four.
13. The parallel successive-approximation analog-to-digital converter according to claim 12, wherein the fine reference-voltage generation unit comprises a resistor string.
14. The parallel successive-approximation analog-to-digital converter of claim 1, wherein the parallel successive-approximation analog-to-digital converter is included in an integrated circuit.
15. The parallel successive-approximation analog-to-digital converter of claim 1, wherein the parallel successive-approximation analog-to-digital converter is included in an electronic apparatus.
16. The parallel successive-approximation analog-to-digital converter according to claim 15, wherein the electronic apparatus is a television set, a liquid-crystal display, a computer monitor, a digital camera, a projector, or a radio receiver.
17. The parallel successive-approximation analog-to-digital converter of claim 10, where the parallel successive-approximation analog-to-digital converter is included in an integrated circuit.
18. The parallel successive-approximation analog-to-digital converter of claim 10, where the parallel successive-approximation analog-to-digital converter is included in an integrated circuit.
19. The parallel successive-approximation analog-to-digital converter of claim 1, wherein the reference-voltage selection unit comprises one or more intermediate switch layers of switch devices operatively connected between the first switch layer and the second switch layer for selectably connecting switch devices in the first switch layer to the corresponding common node.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A data processing system for a graphical interface comprising at least one graphics processing unit (GPU) and at least one central processing unit (CPU) which communicates with the graphics processing unit, said processing unit and said central processing unit each including a group of data processing cores, wherein the data processing cores of the graphics processing unit are each connected to a data processing core of the central processing unit via a single dedicated data transfer means in such a way as to carry out a data transfer in parallel between said graphics processing unit and said central processing unit.
2. The system according to claim 1, wherein at least some of the data processing cores each comprise at least one processing core performing the execution of instructions on the data and a local internal data transfer means connected to peripheral devices, each dedicated to one processing core.
3. The system according to claim 2, wherein the data processing cores are interconnected via a global internal data transfer means to said graphics processing unit or to said central processing unit and are connected to peripheral devices shared between the data processing cores.
4. The system according to claim 3, further comprising arbitration means to arbitrate access to the peripheral devices shared among the data processing cores.
5. The system according to claim 1, further comprising a global operating system shared among a plurality of processing cores.
6. The system according to claim 1, further comprising means for combining the outputs of each processing core of the graphics processing unit.
7. A graphical interface for an aircraft cockpit comprising a data processing system comprising at least one graphics processing unit (GPU) and at least one central processing unit (CPU) which communicates with the graphics processing unit, said processing unit and said central processing unit each including a group of data processing cores, wherein the data processing cores of the graphics processing unit are each connected to a data processing core of the central processing unit via a single dedicated data transfer means in such a way as to carry out a data transfer in parallel between said graphics processing unit and said central processing unit.
8. The graphical interface according to claim 7, wherein at least some of the data processing cores each comprise at least one processing core performing the execution of instructions on the data and a local internal data transfer means connected to peripheral devices, each dedicated to one processing core.
9. The graphical interface according to claim 7, wherein the data processing cores are interconnected via a global internal data transfer means to said graphics processing unit or to said central processing unit and are connected to peripheral devices shared between the data processing cores.
10. The graphical interface according to claim 9, further comprising arbitration means to arbitrate access to the peripheral devices shared among the data processing cores.
11. The graphical interface according to claim 7, further comprising a global operating system shared among a plurality of processing cores.
12. The graphical interface according to claim 7, further comprising means for combining the outputs of each processing core of the graphics processing unit.