1. A compound having a structure according to Formula (Vc):
wherein
R1a is a member selected from H, alkyl, and
where n is an integer from 0 to 3,
R5a, R5b and R5c are members independently selected from H, C1 to C4 alkyl, C1 to C4 alkyne, nitrile, Br, Cl, F, OR18a, furan, tetrahydrofuran, and pyrrole,
R18a is a member selected from H and C1 to C4 alkyl,
R6 is a member selected from OH and O\u2212X+, wherein X+ is a cation,
and any enantiomer, diastereoisomer, racemic mixture, enantiomerically enriched mixture, and enantiomerically pure form thereof.
2. A composition comprising a first stereoisomer and at least one additional stereoisomer of a compound according to claim 1, wherein said first stereoisomer is present in an enantiomeric or diastereomeric excess of at least 90% relative to said at least one additional stereoisomer.
3. A pharmaceutical composition comprising a compound of claim 1, or a pharmaceutically acceptable salt thereof, and a pharmaceutically acceptable carrier.
4. A compound having a structure according to Formula (IVc):
wherein
R1a is a member selected from H, alkyl, and
where n is an integer from 0 to 3,
R5a, R5b and R5c are members independently selected from H, C1 to C4 alkyl, C1 to C4 alkyne, nitrile, Br, Cl, F, OR18a, furan, tetrahydrofuran, and pyrrole,
R18a is a member selected from H and C1 to C4 alkyl,
R6 is a member selected from OH and O\u2212X+, wherein X+ is a cation,
and any enantiomer, diastereoisomer, racemic mixture, enantiomerically enriched mixture, and enantiomerically pure form thereof.
5. A composition comprising a first stereoisomer and at least one additional stereoisomer of a compound according to claim 4, wherein said first stereoisomer is present in an enantiomeric or diastereomeric excess of at least 90% relative to said at least one additional stereoisomer.
6. A pharmaceutical composition comprising a compound of claim 4, or a pharmaceutically acceptable salt thereof, and a pharmaceutically acceptable carrier.
7. A compound having a structure according to Formula (VIIb):
wherein
R30a and R31a are members independently selected from H, C1 to C4 alkyl, and
where n is an integer from 0 to 3,
R5a, R5b and R5c are members independently selected from H, C1 to C4 alkyl, C1 to C4 alkyne, nitrile, Br, Cl, F, and OR18a,
R18a is a member selected from H and C1 to C4 alkyl,
R6 is a member selected from OH and O\u2212X+, wherein X+ is a cation,
and any enantiomer, diastereoisomer, racemic mixture, enantiomerically enriched mixture, and enantiomerically pure form thereof.
8. A composition comprising a first stereoisomer and at least one additional stereoisomer of a compound according to claim 7, wherein said first stereoisomer is present in an enantiomeric or diastereomeric excess of at least 90% relative to said at least one additional stereoisomer.
9. A pharmaceutical composition comprising a compound of claim 7, or a pharmaceutically acceptable salt thereof, and a pharmaceutically acceptable carrier.
10. A compound having a structure according to Formula (VIIIb):
wherein
R30a and R31a are members independently selected from H, C1 to C4 alkyl, and
where n is an integer from 0 to 3,
R5a, R5b and R5c are members independently selected from H, C1 to C4 alkyl, C1 to C4 alkyne, nitrile, Br, Cl, F, and OR18a,
R18a is a member selected from H and C1 to C4 alkyl,
R6 is a member selected from OH and O\u2212X+, wherein X+ is a cation,
and any enantiomer, diastereoisomer, racemic mixture, enantiomerically enriched mixture, and enantiomerically pure form thereof.
11. A composition comprising a first stereoisomer and at least one additional stereoisomer of a compound according to claim 10, wherein said first stereoisomer is present in an enantiomeric or diastereomeric excess of at least 90% relative to said at least one additional stereoisomer.
12. A pharmaceutical composition comprising a compound of claim 10, or a pharmaceutically acceptable salt thereof, and a pharmaceutically acceptable carrier.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processor comprising:
a plurality of cores, wherein at least a first core of the plurality of cores comprises a fetch logic to fetch instructions, a decode logic to decode the instructions, and execution logic to execute the instructions;
a cache memory; and
logic to:
dynamically set, for a platform comprising the processor and a memory module, a power limit for the processor and another power limit for the memory module based on a power budget for the platform, wherein the power limit for the processor is to be set to at least a minimum allowed power consumption of the processor;
analyze an average power consumption of the processor;
analyze another average power consumption of the memory module; and
adjust a power consumption of at least one of the processor and the memory module to enforce the power budget.
2. The processor of claim 1, wherein the logic is to set the power limit for the processor as a difference of the power budget for the platform and the another power limit for the memory module.
3. The processor of claim 1, wherein the logic is further to determine a time period to enforce the power budget for the platform, and to dynamically set the power limit for the processor and the another power limit for the memory module based on the power budget for the platform for a duration of the time period.
4. The processor of claim 3, further comprising a first storage to store the time period.
5. The processor of claim 4, further comprising a second storage to store the power budget for the platform.
6. The processor of claim 1, wherein the logic is to determine the power limit for the processor according to one or more of:
a number of stall counts of the processor; and
characteristics of workloads executed by the processor.
7. The processor of claim 1, wherein the logic to determine the power limit for the memory module according to memory bandwidth utilization of the memory module.
8. The processor of claim 1, wherein the logic is to adjust the power consumption of the processor by adjustment of one or more of, a voltage, a frequency, instruction throughput, and a performance level of code, of the processor.
9. The processor of claim 1, wherein the logic is to adjust the power consumption of the memory module by adjustment of one or more of, read operations, write operations, and a voltage, of the memory module.
10. The processor of claim 1, wherein the processor further comprises a graphics processor.
11. The processor of claim 1, wherein the processor further comprises a power control unit.
12. The processor of claim 1, wherein the processor further comprises a memory controller.
13. A system comprising:
a logic module; and
a processor coupled with the logic module, to:
dynamically set, for the system, a power limit for the processor and another power limit for the logic module based on a power budget for the system, wherein the power limit for the processor is to be set to at least a minimum allowed power consumption of the processor;
analyze an average power consumption of the processor;
analyze another average power consumption of the logic module; and
adjust a power consumption of at least one of the processor and the logic module to enforce the power budget.
14. The system of claim 13, wherein the processor is further to determine a time period to enforce the power budget for the system, and to dynamically set the power limit for the processor and the another power limit for the logic module based on the power budget for the system for a duration of the time period.
15. The system of claim 13, wherein the processor is to adjust the power consumption of the processor according to one or more of adjustment of a voltage, a frequency, instruction throughput, and a performance level of code, of the processor.
16. The system of claim 13, wherein the processor is to determine the power limit for the logic module according to bandwidth utilization of the logic module.
17. The system of claim 13, wherein the logic module comprises one of a memory module, a graphics processor unit (GPU), and a co-processor.
18. A non-transitory machine readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
dynamically setting, for a platform comprising a processor and a memory module, a power limit for the processor and another power limit for the memory module based on a power budget for the platform, wherein the power limit for the processor is to be set to at least a minimum allowed power consumption of the processor;
analyzing an average power consumption of the processor;
analyzing another average power consumption of the memory module; and
adjusting a power consumption of at least one of the processor and the memory module to enforce the power budget.
19. The non-transitory machine readable medium of claim 18, wherein the method further comprises setting the power limit for the processor as a difference of the power budget for the platform and the another power limit for the memory module.
20. The non-transitory machine readable medium of claim 18, wherein the method further comprises determining the power limit for the processor according to one or more of:
a number of stall counts of the processor; and
characteristics of workloads executed by the processor.