1. Light-scattering methacrylic polymer material comprising:
from 80 to 90 percent by weight of a methacrylic (co)polymer containing predominantly methyl methacrylate units;
from 5 to 15 percent by weight of a fire retardant compatible with the methyl methacrylate monomer and the methacrylic (co)polymer, the said fire retardant being chosen from a halogenated polyphosphonate compound, a halogenated neutral ester compound of phosphoric acid or a mixture of these two compounds; and
from 1 to 5 percent by weight of silica having an elementary particle size of less than 500 nm.
2. The polymer material of claim 1 wherein said silica has an elementary particle size of less than 100 nm.
3. The polymer material according to claim 1, characterized in that the methacrylic (co)polymer employed is a methyl methacrylate homopolymer.
4. The polymer material according to claim 1, characterized in that the halogenated polyphosphonate compound used is a chlorinated polyphosphonate.
5. The polymer material according to claim 1, characterized in that the halogenated neutral ester of phosphoric acid is tris(2-chloroisopropyl) phosphate.
6. The polymer material according to claim 1, characterized in that the silica is a precipitated silica.
7. The polymer material according to claim 1, characterized in that the silica has an elementary particle size of less than 15 nm.
8. The polymer material according to claim 7, characterized in that the silica has an elementary particle size of less than 10 nm.
9. The polymer material according to claim 1, characterized in that it comprises:
from 82 to 86 percent by weight of the methacrylic (co)polymer;
from 10 to 12 percent by weight of the fire retardant; and
from 2 to 4 percent by weight of precipitated silica.
10. The polymer material according to claim 9 characterized in that it comprises:
from 82 to 86 percent by weight of the methacrylic (co)polymer;
from 10 to 12 percent by weight of TCIP;
from 2 to 4 percent by weight of silica RP 635.
11. The polymer material according to claim 1, characterized in that it is in the form of sheets.
12. The polymer material according to claim 11, characterized in that the sheets have a thickness of between 2.5 and 8 mm.
13. The polymer material according to claim 12, characterized in that the sheets have a thickness of between 3 and 6 mm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power saving method applied to a CPU that is in a C3 state and a peripheral device issues a bus master request, comprising the steps of:
asserting a stop signal to prohibit said CPU from fetching instructions;
asserting a first control signal to drive said CPU leaving said C3 state; and
asserting a second control signal to drive said CPU entering a C2 state;
wherein said CPU returns to said C3 state after leaving said C2 state.
2. The method as claimed in claim 1, wherein said stop signal is asserted by a pin disposed in a system chip to a corresponding pin of said CPU.
3. The method as claimed in claim 1, further comprises a step of enabling an arbiter to transfer said bus master request to said CPU after said CPU is in C2 state.
4. The method as claimed in claim 3, wherein after said CPU completes said bus master request, further comprises:
disabling said arbiter;
asserting a third control signal to drive said CPU leaving said C2 state; and
asserting a fourth control signal to drive said CPU returning to said C3 state.
5. The method as claimed in claim 4, wherein said steps of asserting said first control signal, said second control signal, said third control signal and said fourth control signal are driven by a power management unit of a system chip.
6. The method as claimed in claim 4, wherein said CPU transits to a C0 state after leaving said C2 state, and transits to said C0 state after leaving said C3 state.
7. The method as claimed in claim 4, wherein after said CPU returns to said C3 state and said peripheral device issues an interrupt event, further comprises:
asserting said first control signal to drive said CPU leaving said C3 state and entering a C0 state;
asserting a resume signal to said CPU; and
enabling said arbiter to transfer said interrupt event to said CPU for processing.
8. The method as claimed in claim 4, wherein after said CPU returns to said C3 state and said peripheral device issues said bus master request again, asserting said first control signal and said second control signal to said CPU and enabling said arbiter to snoop said bus master request; after said bus master request is completed, disabling said arbiter and asserting said third control signal and said fourth control signal to said CPU.
9. A power saving method applied to a CPU that is in a non-snooping sleeping state and a peripheral device issues a bus master request, comprising the steps of:
asserting a stop signal to prohibit said CPU from fetching instructions;
asserting a first control signal to drive said CPU leaving said non-snooping sleeping state; and
asserting a second control signal to drive said CPU entering a snooping sleeping state that allows snooping function;
wherein said CPU transits to a normal processing state after leaving said snooping sleeping state.
10. The method as claimed in claim 9, wherein said stop signal is asserted by a pin disposed in a system chip to a corresponding pin of said CPU.
11. The method as claimed in claim 9, further comprises a step of enabling an arbiter to transfer said bus master request to said CPU after said CPU is in snooping sleeping state.
12. The method as claimed in claim 11, wherein after said CPU completes said bus master request, further comprises:
disabling said arbiter;
asserting a third control signal to drive said CPU leaving said snooping sleeping state; and
asserting a fourth control signal to drive said CPU returning to said non-snooping sleeping state.
13. The method as claimed in claim 12, wherein said CPU transits to said normal processing state after leaving said snooping sleeping state.
14. The method as claimed in claim 12, wherein said steps of asserting said first control signal, said second control signal, said third control signal and said fourth control signal are driven by a power management unit of a system chip.
15. The method as claimed in claim 12, wherein after said CPU returns to said non-snooping sleeping state and said peripheral device issues an interrupt event, further comprises:
asserting said first control signal to drive said CPU leaving said non-snooping sleeping state and entering said normal processing state;
asserting a resume signal to said CPU; and
enabling said arbiter to transfer said interrupt event to said CPU for processing.
16. The method as claimed in claim 12, wherein after said CPU returns to said non-snooping sleeping state and said peripheral device issues said bus master request again, asserting said first control signal and said second control signal to said CPU and enabling said arbiter to snoop said bus master request; after said bus master request is completed, disabling said arbiter and asserting said third control signal and said fourth control signal to said CPU.
17. The method as claimed in claim 9, wherein said non-snooping sleeping state is C3 state and said snooping sleeping state is C2 state and said normal processing state is C0 state.