1. A buckle comprising:
a socket and a plug,
wherein the socket comprises: a cylindrical main body having an insertion port into which the plug is can be inserted at one end and an attachment to which a corded member is attachable at another end; a hollow part formed within the main body; a pair of left and right openings continuous to the hollow part and penetrating through wall parts of the main body; and a pair of left and right first latch surfaces defined on opening-side wall surfaces of the wall parts of the main body and exposed from the openings to the attachment, the opening-side wall surfaces inclined in a direction intersecting with an insertion direction of the plug,
wherein the plug comprises: a base to which a corded member is attachable; a pair of left and right arms extended from one end of the base; and a pair of left and right second latch surfaces protruding outward from outer sides of the arms, respectively, and inclined in the direction intersecting with the insertion direction of the plug, respectively, the second latch surfaces engagable with the first latch surfaces,
and wherein inner ends of the second latch surfaces are brought into contact with lines that extend in parallel to the insertion direction of the plug and pass through inner side portions located at outermost portions on inner sides of proximal ends of the arms, or disposed further inside the lines.
2. The buckle of claim 1, wherein an inclination angle \u03b8 of each of the second latch surfaces is between 10 degrees and 20 degrees.
3. The buckle of claim 1, wherein the buckle has a minimum tensile strength of 1335N or more and a release load of between 15 N and 25 N.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of performing a multi-register scatter instruction in a computer processor, comprising:
fetching the multi-register scatter instruction that includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes a plurality of source data elements, wherein the destination operand identifies a first plurality of destination data elements, wherein each of the destination data elements specifies a destination vector register and an index into that destination vector register;
decoding the fetched multi-register scatter instruction; and
executing the decoded multi-register scatter instruction causing, for each of the first plurality of destination data elements, the one of the source data elements that is in a position in the source vector register that corresponds with a position of that destination data element to be stored in the destination vector register at the index specified by that destination data element.
2. The method of claim 1, wherein the destination operand specifies a vector register that identifies the first plurality of destination data elements.
3. The method of claim 2, wherein the vector register specified by the destination operand includes a second plurality of destination data elements that includes the first plurality of destination data elements and at least one destination data element that indicates that the one of the source data elements that is in a position in the source vector register that corresponds with that destination data element is not to be stored in a destination vector register as a result of executing the decoded multi-register scatter instruction.
4. The method of claim 2, wherein the source vector register and the vector register specified by the destination operand are each 512-bits.
5. The method of claim 4, wherein each of the first plurality of destination data elements is 32-bits of which 8 bits indicate a destination vector register and 8 bits indicate an index into that destination vector register.
6. The method of claim 1, wherein the destination operand specifies a memory location that identifies the first plurality of destination data elements.
7. The method of claim 1, wherein the source vector register is 512-bits.
8. A processor core, comprising:
a hardware decode unit to decode a multi-register scatter instruction, wherein the multi-register scatter instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes a plurality of source data elements, wherein the destination operand identifies a first plurality of destination data elements, wherein each of the destination data elements specifies a destination vector register and an index into that destination vector register; and
an execution engine unit to execute the decoded multi-register scatter instruction which causes, for each of the first plurality of destination data elements, the one of the source data elements that is in a position in the source vector register that corresponds with a position of that destination data element to be stored in the destination vector register at the index specified by that destination data element.
9. The processor core of claim 8, wherein the destination operand specifies a vector register that identifies the first plurality of destination data elements.
10. The processor core of claim 9, wherein the vector register specified by the destination operand includes a second plurality of destination data elements that includes the first plurality of destination data elements and at least one destination data element that indicates that the one of the source data elements that is in a position in the source vector register that corresponds with that destination data element is not to be stored in a destination vector register as a result of executing the decoded multi-register scatter instruction.
11. The processor core of claim 9, wherein the source vector register and the vector register specified by the destination operand are each 512-bits.
12. The processor core of claim 11, wherein each of the first plurality of destination data elements is 32-bits of which 8 bits indicate a destination vector register and 8 bits indicate an index into that destination vector register.
13. The processor core of claim 8, wherein the destination operand specifies a memory location that identifies the first plurality of destination data elements.
14. The processor core of claim 8, wherein the source vector register is 512-bits.
15. An article of manufacture, comprising:
a tangible machine-readable storage medium having stored thereon a multi-register scatter instruction, wherein the multi-register scatter instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes a plurality of source data elements, wherein the destination operand identifies a first plurality of destination data elements, wherein each of the destination data elements specifies a destination vector register and an index into that destination vector register; and
wherein the multi-register scatter instruction includes an opcode, which instructs a machine to execute the instruction that causes, for each of the first plurality of destination data elements, the one of the source data elements that is in a position in the source vector register that corresponds with a position of that destination data element to be stored in the destination vector register at the index specified by that destination data element.
16. The article of manufacture of claim 15, wherein the destination operand specifies a vector register that identifies the first plurality of destination data elements.
17. The article of manufacture of claim 16, wherein the vector register specified by the destination operand includes a second plurality of destination data elements that includes the first plurality of destination data elements and at least one destination data element that indicates that the one of the source data elements that is in a position in the source vector register that corresponds with that destination data element is not to be stored in a destination vector register as a result of executing the decoded multi-register scatter instruction.
18. The article of manufacture of claim 16, wherein the source vector register and the vector register specified by the destination operand are each 512-bits.
19. The article of manufacture of claim 18, wherein each of the first plurality of destination data elements is 32-bits of which 8 bits indicate a destination vector register and 8 bits indicate an index into that destination vector register.
20. The article of manufacture of claim 15, wherein the destination operand specifies a memory location that identifies the first plurality of destination data elements.