1. A method of manufacturing an image sensor, comprising:
providing a substrate including a first area and a second area, wherein a photodiode is formed in the first area of the substrate and the second area surrounds the first area;
forming an insulation pattern structure making contact with the photodiode in the first area of the substrate;
forming an anti-reflection layer on the insulation pattern structure and on the substrate;
forming a preliminary insulation interlayer structure having a plurality of insulation layers on the anti-reflection layer and on the substrate, the preliminary insulation interlayer structure including a first metal wiring structure in the first area and a second metal wiring structure in the second area, wherein a top surface of the second metal wiring structure in the second area is above that of the first metal wiring structure in the first area;
forming a recess portion in the first area of the substrate by partially etching the preliminary insulation interlayer structure, to form a first preliminary insulation interlayer structure on the first area of the substrate and form a second preliminary insulation interlayer structure on the second area of the substrate;
partially etching the first preliminary insulation interlayer structure and the anti-reflection layer corresponding to the photodiode, to form a first insulation interlayer structure having a second opening and form an anti-reflection pattern having a first opening connected to the second opening;
forming a transparent insulation pattern in the first and second openings;
forming a color filter on the transparent insulation pattern; and
forming a micro lens on the color filter.
2. The method of claim 1, further comprising, after forming the second metal wiring structure, forming a pad electrode on the top surface of the second metal wiring structure, wherein signals fromto the image sensor transfer through the electrode pad.
3. The method of claim 1, wherein the first and second metal wiring structures comprise copper.
4. The method of claim 1, wherein forming the transparent insulation pattern includes:
forming a transparent insulation layer on a bottom portion of the recess portion to a thickness to fill the first and second openings; and
etching the transparent insulation layer until the bottom portion of the recess portion is exposed and the transparent insulation layer only remains in the first and second openings.
5. The method of claim 1, wherein forming the preliminary insulation interlayer structure includes:
forming a first insulation interlayer on the substrate;
forming a first subsidiary wiring in the first insulation interlayer, the first subsidiary wiring making contact with a first contact plug formed at a lower portion thereof;
forming a second insulation interlayer on the first insulation interlayer and the first subsidiary wiring;
forming second contact plugs making contact with the first subsidiary wiring in the second insulation interlayer;
forming a third insulation interlayer on the second insulation interlayer and the second contact plugs;
forming a second subsidiary wiring making contact with the second contact plug in the third insulation interlayer;
forming a fourth insulation interlayer on the third insulation interlayer and the second subsidiary wiring;
forming third contact plugs making contact with the second subsidiary wiring penetrating the fourth insulation interlayer in the second area of the substrate;
forming a fifth insulation interlayer on the fourth insulation interlayer and the third contact plug;
forming a third subsidiary wiring making contact with the third contact plug in the fifth insulation interlayer;
forming a sixth insulation interlayer on the fifth insulation interlayer and the third subsidiary wiring;
forming fourth contact plugs making contact with the third subsidiary wiring in the sixth insulation interlayer;
forming a seventh insulation interlayer on the sixth insulation interlayer and the fourth contact plug; and
forming a fourth subsidiary wiring making contact with the fourth contact plug in the seventh insulation interlayer.
6. The method of claim 5, further comprising forming first through sixth etching stop layers on each boundary surface of the first through seventh insulation interlayers, the etching stop layer comprising a non-transparent material.
7. The method of claim 1, further comprising, prior to forming the insulation pattern structure, forming a transistor on the substrate.
8. The method of claim 7, wherein forming the insulation pattern structure includes:
sequentially forming a silicon oxide layer and a silicon nitride layer on the substrate;
forming a photoresist pattern on the silicon nitride layer, the first area in which the photodiode is formed is covered with the photoresist pattern and the second area is exposed through the photoresist pattern; and
anisotropically etching the silicon nitride layer and the silicon oxide layer using the photoresist pattern as an etching mask.
9. The method of claim 8, wherein a first spacer comprising silicon oxide and a second spacer comprising silicon nitride are formed on a sidewall of a gate electrode of the transistor in the anisotropic etching process.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic assembly comprising:
a copper pillar attach substrate comprising:
a dielectric layer;
a solder resist layer overlying said dielectric layer, said solder resist layer having a plurality of openings therein and having a solder resist layer thickness; and
a plurality of parallel traces formed on said dielectric layer, each trace having a first end portion, a second end portion and an intermediate portion, said first and second end portions being covered by said solder resist layer, said intermediate portions being positioned in said openings in said solder resist layer, each of said intermediate portions having at least one conductive coating layer thereon and having a height measured from said dielectric layer to a topmost one of said at least one conductive coating layer that is at least as great as said solder resist layer thickness.
2. The electronic assembly of claim 1, said at least one conductive coating layer comprising a first conductive coating layer and a second conductive coating layer.
3. The electronic assembly of claim 2, said first conductive coating layer comprising copper.
4. The electronic assembly of claim 2, said second conductive coating layer comprising tin.
5. The electronic assembly of claim 1, said traces comprising copper.
6. The electronic assembly of claim 1, said openings in said solder resist layer being staggered.
7. The electronic assembly of claim 1, adjacent ones of said plurality of parallel traces being separated by a trace spacing distance, said solder resist layer openings being staggered, and further comprising a die having a plurality of copper pillars, each of said copper pillars having a tip portion connected to said intermediate portion of an associated one of said plurality of traces; each of said copper pillars having a cross sectional dimension measured perpendicular to said parallel traces that is greater than a dimension of an associated one of said solder resist openings measured perpendicular to said parallel traces.
8. The electronic assembly of claim 7 said tip portion of each of said copper pillars being bonded to said at least one coating layer on said intermediate portion of an associated one of said plurality of traces.
9. The electronic assembly of claim 8, said at least one conductive coating layer on said intermediate portion of each of said plurality of traces comprising a first coating layer and second coating layer over said first coating layer, said tip portion of said copper pillar being bonded to said second coating layer.
10. The electronic assembly of claim 9, said first coating layer being thicker than said second coating layer.
11. The electronic assembly of claim 7, said tip portions each having a circular cross section.
12. The electronic assembly of claim 1 said plurality of parallel traces being positioned in an area defined by a first line perpendicular to said traces and intersecting an outermost one of said trace first end portions and a second line perpendicular to said traces and intersecting an outermost one of said trace second end portions and wherein said plurality of traces each has a length less than distance between said first line and said second line.
13. The electronic assembly of claim 12 wherein said plurality of traces each has a length less than one half the distance between said first line and said second line.
14. The electronic assembly of claim 12 wherein said layer of solder resist extends at least to said first line and to said second line in a region extending from at least a first one of said plurality of parallel traces to at least a last one of said plurality of parallel traces.
15. An electronic assembly comprising:
a copper pillar attach substrate comprising:
a dielectric layer;
a solder resist layer overlying said dielectric layer, said solder resist layer having a plurality of openings therein and having a solder resist layer thickness; and
a plurality of parallel traces formed on said dielectric layer, each trace having a first end portion, a second end portion and an intermediate portion, said first and second end portions being covered by said solder resist layer, said intermediate portions being positioned in said openings in said solder resist layer, said plurality of parallel traces being positioned in an area defined by a first line perpendicular to said traces and intersecting an outermost one of said trace first end portions and a second line perpendicular to said traces and intersecting an outermost one of said trace second end portions and wherein said plurality of traces each has a length less than the distance between said first line and said second line.
16. The electronic assembly of claim 15 wherein adjacent ones of said plurality of parallel traces have no lengthwise overlap.
17. The electronic assembly of claim 15 wherein said openings in said solder resist layer are arranged in parallel rows extending transversely to said traces.
18. A method of forming a copper pillar attach substrate comprising:
providing a substrate with a dielectric layer;
forming a plurality of parallel traces on the dielectric layer;
applying a solder resist layer over the plurality of parallel traces,
forming openings in the solder resist layer that exposes an intermediate portion of each trace; and
coating the exposed intermediate portion of each of the traces with conductive material that extends to a height above the height of the solder resist layer.
19. The method of claim 18 wherein said forming a plurality of parallel traces on the dielectric layer comprises staggering the starting points and the ending points of the parallel traces such that no portion of the lengths of adjacent parallel traces are positioned laterally opposite one another.
20. The method of claim 18 wherein said forming openings in the solder resist layer that exposes an intermediate portion of each trace comprises forming staggered openings.