1. A method for producing a semiconductor optical device, the method comprising the steps of:
forming a semiconductor region on a substrate, the semiconductor region including a ridge structure;
forming an insulating film on the semiconductor region;
forming a non-photosensitive resin region on the insulating film, the non-photosensitive resin region having an opening on an upper surface of the ridge structure, the ridge structure being embedded with the non-photosensitive resin region;
forming a first mask on the non-photosensitive resin region, the first mask having an opening that defines a scribe area;
forming the scribe area by etching the non-photosensitive resin region using the first mask until the insulating film is exposed;
after removing the first mask, forming an insulating layer by etching the insulating film using the non-photosensitive resin region as a mask, the insulating layer having a first opening on the upper surface of the ridge structure and a second opening in the scribe area;
forming an electrode in the first opening of the insulating layer on the ridge structure and the non-photosensitive resin region to produce a substrate product;
forming a scribe line on a surface of the semiconductor region in the scribe area of the substrate product; and
cutting the substrate product along the scribe line to form a semiconductor laser bar,
wherein the second opening of the insulating layer in the scribe area is located outside a device region for the semiconductor optical device, and
the electrode is in direct contact with the upper surface of the ridge structure through the first opening of the insulating layer.
2. The method according to claim 1, wherein, in the step of forming the scribe area, the non-photosensitive resin region is etched by reactive ion etching using a mixed gas containing fluorocarbon and oxygen.
3. The method according to claim 1,
wherein the step of forming the non-photosensitive resin region includes the steps of:
forming a non-photosensitive resin on the entire surface of the semiconductor region;
forming a second mask on the non-photosensitive resin, the second mask having an opening above the upper surface of the ridge structure;
forming the non-photosensitive resin region by etching the non-photosensitive resin using the second mask; and
removing the second mask.
4. The method according to claim 1, wherein, in the step of forming the non-photosensitive resin region, the thickness of the non-photosensitive resin region is less than 2.0 \u03bcm on the ridge structure.
5. The method according to claim 1, wherein the scribe area extends in a direction crossing an extending direction of the ridge structure, and the width of the scribe area is 5 \u03bcm or more.
6. The method according to claim 1,
wherein the first mask also has first and second openings that extend in an extending direction of the ridge structure,
the non-photosensitive resin region has first and second stripe-shape openings defined by the first and second openings of the first mask, respectively,
the opening of the non-photosensitive resin region is formed between the first and second stripe-shape openings, and
the method further comprises a step of separating the semiconductor laser bar into individual semiconductor optical devices at positions of the first and second stripe-shape openings.
7. The method according to claim 1,
wherein the step of forming the semiconductor region further includes the steps of;
forming an epitaxial wafer including a plurality of semiconductor layers grown on the substrate; and
forming first and second trenches that define the ridge structure by etching the epitaxial wafer using a trench mask,
the insulating layer covers side surfaces of the ridge structure and surfaces of the first and second trenches,
the first and second trenches are filled with the non-photosensitive resin region,
the non-photosensitive resin region covers the insulating layer located on the side surfaces of the ridge structure,
the first trench is defined by a first protruding portion and the ridge structure,
the second trench is defined by a second protruding portion and the ridge structure,
the semiconductor region includes the first protruding portion, the second protruding portion, and the ridge structure, and
the thickness of the non-photosensitive resin region is 1.5 \u03bcm or less on the first and second protruding portions.
8. The method according to claim 1, wherein, in the step of forming the scribe line, the scribe line has a trench shape.
9. The method according to claim 1,
wherein, in the step of forming the semiconductor laser bar, an end face of the semiconductor laser bar formed by cutting the substrate product extends from an edge of a back of the substrate to an edge of an upper surface of the non-photosensitive resin region, and
the end face of the semiconductor laser bar includes cleavage planes formed in the substrate and the semiconductor region and a fracture surface formed in the non-photosensitive resin region.
10. The method according to claim 1, wherein the non-photosensitive resin region is composed of a non-photosensitive bisbenzocyclobutene resin.
11. The method according to claim 1, wherein the non-photosensitive resin region is composed of a non-photosensitive polymer containing silicon.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for optimizing circuits having a congested placement with a timing critical placement map comprising:
using a computer,
determining non-critical circuit components safe to be moved wherein non-critical circuit components are circuits in which a change to its physical placement will not degrade the timing below an acceptable threshold or introduce a new timing violation;
removing all non-critical circuit components from said timing critical placement map to generate a new partial placement map;
optimizing critical circuit components in said new partial placement map free of all of said non-critical circuit components wherein said critical circuit components are a set of circuit components that are not non-critical circuit components;
inserting new circuit components to replace failing critical circuit components; and reinserting all of said non-critical circuit components that were previously removed from said timing critical placement map into said new partial placement map.
2. The method of claim 1 wherein said optimization is performed by circuit transformation operating in congested regions of said placement map enabling cell insertion and modifications that increase a cell size.
3. The method of claim 2 further comprising operating on timing said critical circuit components and on difficult paths while preserving said timings surrounding said critical circuit components.
4. The method of claim 1 further comprising:
finding open exact placement locations in a congested placement map free of all of the non-critical circuit components for buffer insertion or cell size manipulation;
improving hold timing take-down while limiting side effects to critical setup slacks; and
creating a seamless mechanism allowing newly inserted and manipulated cells to automatically displace non-critical cells.
5. The method of claim 1 further comprises providing a timing critical placement image map for said optimization.
6. The method of claim 5 wherein said timing critical image map enables said critical-circuit components present in said placement image map remain locked in place during subsequent placement image legalizations.
7. The method of claim 1 further comprising incorporating a combination that provides flexibility for an estimated placement model.
8. The method of claim 1, wherein timing a critical-only incremental placement model puts a hold on a timing violation repair, said hold timing closure being deferred until after setup timing optimization is performed.
9. The method of claim 1, wherein setup timing closures restricts or fragments said placement map, and wherein said hold inhibits said optimization from inserting or modifying said failing circuit components in said placement map to repair violations.
10. The method of claim 1, wherein less critical circuit components are moved at behest of critical paths requiring image resource and placement precision of an exact model for said critical circuit components under optimization.
11. The method of claim 1 wherein circuit transformation optimizations operate in congested regions of said placement image map, enabling cell insertion and modifications that increase cell size which will otherwise be prohibited due to placement constraints.
12. The method of claim 10, further comprising enabling said optimizations determine an accurate timing that is afforded by obtaining legal physical placement locations.
13. The method of claim 11, wherein said circuit transformation optimizations operate on said timing critical circuit components and progress on difficult paths.
14. The method of claim 11 wherein said optimizing is performed while preserving the timing of surrounding said critical circuit components.
15. The method of claim 1, further comprising:
locking and fixing the critical circuit components, said critical circuit components include the inserted new circuit components;
legalizing said non-critical circuit components which are unlocked while the critical circuit components are locked, the locking of the critical components prevents the legalizing step from changing the placements of the critical circuit components; and
unlocking and reverse fixing the critical circuit components.
16. The method of claim 15 further comprising legalizing said placement images by resolving overlaps.
17. The method of claim 15 wherein said legalizing is achieved using smooth-spreading techniques for minimizing magnitudes of individual cell displacements.
18. The method of claim 1 further comprising locking cell placements of all of said critical circuit components in a chip image, wherein a critical circuit includes all other circuits not encountered in said set of non-critical circuits.
19. The method of claim 18 wherein said locking said cell placements of said critical circuit components prevents future legalizations from changing the cell placements of said circuits ensuring that their timing does not degrade, and wherein new cells inserted into said placement map are also in said set of critical cells.
20. The method of claim 18 further comprising restoring original placement characteristics of said cells by removing any of said cell locks or fix-in-place directives previously applied.
21. A non-transitory storage medium for storing optimized circuits having a congested placement with a timing critical placement map storing instructions for executing by a processing circuit for performing a method comprising:
determining non-critical circuit components safe to be moved wherein non-critical circuit components are circuits in which a change to its physical placement will not degrade the timing below an acceptable threshold or introduce a new timing violation;
removing all non-critical circuit components from said timing critical placement map to generate a new partial placement map;
optimizing critical circuit components in said new partial placement map free of all of said non-critical circuit components wherein said critical circuit components are a set of circuit components that are not non-critical circuit components;
inserting new circuit components to replace failing critical circuit components; and
reinserting all of said non-critical circuit components that were previously removed from said timing critical placement map into said new partial placement map.