1. A computer-accessible medium which includes a computer program thereon for generating digital information associated with at least one individual, wherein when the computer program is executed by a processing arrangement, the processing arrangement is configured to provide the procedures comprising:
using the processing arrangement, generating a data structure relating to motions of a plurality of individuals; and
using the processing arrangement, generating a plurality of data elements relating to an invariance of the motions across the individuals, wherein the data elements are generated using an orthonormal decomposition of motion data relating to each of the individuals performing one or more of the motions.
2. The computer-accessible medium of claim 1, wherein the orthonormal decomposition is an n-mode singular value decomposition.
3. The computer-accessible medium of claim 1, wherein the motion data includes joint angles.
4. A computer-accessible medium which includes a computer program thereon for generating digital information associated with at least one subject, wherein when the computer program is executed by a processing arrangement, the processing arrangement is configured to provide the procedures comprising:
using the processing arrangement, generating a data structure relating to motions of a plurality of subjects and a plurality of actions; and
using the processing arrangement, generating a plurality of data elements relating to an invariance across each of the actions for at least one respective subject, wherein the data elements are generated using an orthonormal decomposition of motion data relating to each of the subjects performing one or more of the motions.
5. The computer-accessible medium of claim 4, wherein the orthonormal decomposition is an n-mode singular value decomposition.
6. The computer-accessible medium of claim 4, wherein the action data includes joint angles.
7. The computer-accessible medium of claim 1, wherein, when the computer program is executed by the processing arrangement, the processing arrangement is configured to at least one of display or store the digital information in a storage arrangement in at least one of a user-accessible format or a user-readable format, and wherein the digital information includes at least one of the data structure or the plurality of data elements.
8. The computer-accessible medium of claim 4, wherein, when the computer program is executed by the processing arrangement, the processing arrangement is configured to at least one of display or store the digital information in a storage arrangement in at least one of a user-accessible format or a user-readable format, and wherein the digital information includes at least one of the data structure or the plurality of data elements.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of controlling a clock synchronization circuit in a memory device, said method comprising:
receiving a first command to read first data from said memory device;
turning on said clock synchronization circuit to produce an output clock signal in response to said receiving said first command;
synchronizing said output clock signal with a reference clock signal;
reading said first data from said memory device after said synchronizing;
receiving a second command to read second data from said memory device after said reading said first data;
reading said second data from said memory device; and
turning off said clock synchronization circuit after said second reading.
2. The method of claim 1 further comprising delaying said turning off for a fixed period of time after said reading.
3. A method of controlling a clock synchronization circuit in a memory device, said method comprising:
receiving a command to read data from said memory device;
signaling said clock synchronization circuit to turn on in response to said receiving;
locking said clock synchronization circuit to a reference clock signal, where said clock synchronization circuit is locked with said reference clock signal in less time than a column address strobe latency of said memory device;
reading said data from said memory device after said locking; and
signaling said clock synchronization circuit to turn off in response to completion of said reading.
4. The method of claim 3 wherein said receiving comprises receiving a command at memory control logic to read data from said memory device.
5. The method of claim 3 wherein said signaling said clock synchronization circuit to turn on comprises signaling said clock synchronization circuit from memory control logic to turn on said clock synchronization circuit.
6. The method of claim 3 wherein said signaling said clock synchronization circuit to turn off comprises signaling said clock synchronization circuit from memory control logic to turn off said clock synchronization circuit.
7. A method of controlling a clock synchronization circuit in a memory device, said method comprising:
deactivating said clock synchronization circuit;
receiving a first read command;
activating said clock synchronization circuit;
reading first data in accordance with said first read command;
receiving a second read command;
reading second data in accordance with said second read command;
deactivating said clock synchronization circuit in response to completion of said second reading.
8. A memory device comprising:
a memory array operative to store data;
a controller operative to receive commands to read said stored data from said memory array;
a clock synchronization circuit operative to receive a reference clock signal and to output a synchronized clock output signal; and
a signal line coupling said controller to said clock synchronization circuit, said signal line operative to convey signals from said controller to said clock synchronization circuit to turn on said synchronization circuit in response to said controller receiving a read command and to turn off said synchronization circuit after said reading, wherein said synchronization circuit is synchronized in less time than a column address strobe latency of said memory device.
9. A memory device comprising:
a memory array having an array of control inputs operative to receive control signals and having an array of data inputs and outputs, said inputs operative to receive data and said outputs operative to output data;
IO logic having an array of control inputs operative to receive control signals, a first array of data inputs and outputs coupled to said memory array data inputs and outputs, and a second array of data inputs and outputs, said IO logic operative to receive data from said memory array and output said data from said second array, said IO logic also operative to receive data from said second array and output said data to said memory array;
control logic having an array of inputs operative to receive instructions and an array of control outputs, a portion of said outputs coupled to said memory array and a portion of said outputs coupled to said IO logic, said control logic operative to control said memory array and said IO logic;
WRITE logic having an array of data inputs operative to receive data and an array of data outputs operative to transmit data to said IO logic second array; and
READ logic having an array of data inputs operative to receive data from said IO logic second array and an array of data outputs operative to output said data, said READ logic further comprising:
clock synchronization circuit operative to control the timing of said receiving data, wherein said clock synchronization circuit is turned on and off by said control logic and wherein said synchronization circuit is synchronized in less time than a column address strobe latency of said memory device.
10. Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
means for receiving a first command to read first data from said memory device;
means for turning on said clock synchronization circuit to produce an output clock signal in response to said means for receiving said first command;
means for synchronizing said output clock signal with a reference clock signal;
means for reading said first data from said memory device after said synchronizing;
means for receiving a second command to read second data from said memory device after said reading said first data;
means for reading said second data from said memory device; and
means for turning off said clock synchronization circuit after said second reading.
11. The apparatus of claim 10 further comprising means for delaying said turning off for a fixed period of time after said reading.
12. Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
means for receiving a command to read data from said memory device;
means for signaling said clock synchronization circuit to turn on in response to said receiving;
means for locking said clock synchronization circuit to a reference clock signal, where said clock synchronization circuit is locked with said reference clock signal in less time than a column address strobe latency of said memory device;
means for reading said data from said memory device after said locking; and
means for signaling said clock synchronization circuit to turn off in response to completion of reading said data.
13. Apparatus for controlling a clock synchronization circuit in a memory device, said apparatus comprising:
means for deactivating said clock synchronization circuit;
means for receiving a first read command;
means for activating said clock synchronization circuit;
means for reading first data in accordance with said first read command;
means for receiving a second read command;
means for reading second data in accordance with said second read command; and
means for deactivating said clock synchronization circuit in response to completion of said second reading.
14. A system comprising:
a processor;
a memory controller coupled to said processor;
a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller, at least one of said DRAM chips comprising a clock synchronization circuit operative to receive a reference clock signal and to output a synchronized clock output signal;
a plurality of signal buses coupling said processor to said memory controller and said memory controller to said DRAM chips; and
a signal line coupling said memory controller to said clock synchronization circuit, said signal line conveying signals from said memory controller to said clock synchronization circuit to turn said clock synchronization circuit on in response to said controller receiving a read command and to turn said clock synchronization circuit off after said read command is processed, wherein said synchronization circuit is synchronized in less time than a column address strobe latency of said memory device.
15. The system of claim 14 wherein said at least one of said DRAM chips comprises:
a memory array having an array of control inputs operative to receive control signals and having an array of data inputs and outputs, said inputs operative to receive data and said outputs operative to output data;
IO logic having an array of control inputs operative to receive control signals, a first array of data inputs and outputs coupled to said memory array data inputs and outputs, and a second array of data inputs and outputs, said IO logic operative to receive data from said memory array and output said data from said second array, said IO logic also operative to receive data from said second array and output said data to said memory array;
WRITE logic having an array of data inputs operative to receive data and an array of data outputs operative to transmit data to said IO logic second array; and
READ logic having an array of data inputs operative to receive data from said IO logic second array and an array of data outputs operative to output said data.
16. The system of claim 14 wherein said clock synchronization circuit is a synchronous mirror delay.