1. A nonvolatile memory structure comprising:
a semiconductor substrate;
a transistor located on a surface of said semiconductor substrate, said transistor comprising a first dielectric on the surface of said semiconductor substrate, a conducting gate stacked above said first dielectric, and several first doped regions in said semiconductor substrate as a source and a drain thereof, respectively; and
a capacitor located on the surface of said semiconductor substrate, said capacitor comprising a second doped region in said semiconductor substrate, a second dielectric on a surface of said second doped region, and a second conducting gate stacked above said second dielectric, said first and second conducting gates being electrically connected together as a single floating gate.
2. The nonvolatile memory structure as claimed in claim 1, wherein said transistor is a MOSFET.
3. The nonvolatile memory structure as claimed in claim 1, wherein said semiconductor is p-type or n-type.
4. The nonvolatile memory structure as claimed in claim 1, wherein said first doped region and said second doped region are doped with impurities of a first type, while said semiconductor substrate is doped with impurities of a second type, and said first type impurities and said second type impurities are different.
5. The nonvolatile memory structure as claimed in claim 3, wherein if said semiconductor substrate is p-type, then said first doped region and said second doped region are n-type.
6. The nonvolatile memory structure as claimed in claim 4, wherein if said semiconductor substrate is p-type, then said first doped region and said second doped region are n-type.
7. The nonvolatile memory structure as claimed in claim 3, wherein if said semiconductor substrate is n-type, then said first doped region and said second doped region are p-type.
8. The nonvolatile memory structure as claimed in claim 4, wherein if said semiconductor substrate is n-type, then said first doped region and said second doped region are p-type.
9. The nonvolatile memory structure as claimed in claim 1, wherein a third doped region is provided in said semiconductor substrate and below said first doped region, and said third doped region is doped with impurities of the same type with said second doped region.
10. The nonvolatile memory structure as claimed in claim 7, wherein if said semiconductor substrate is n-type, then said second and third doped regions are p-type.
11. The nonvolatile memory structure as claimed in claim 7, wherein if said semiconductor substrate is p-type, then said second and third doped regions are n-type.
12. A method of operating a nonvolatile memory, said nonvolatile memory comprising several first doped regions as a source and a drain and a first conducting gate, and a capacitor structure composed of a second doped region and a second conducting gate on a p-type semiconductor substrate, said first and second conducting gates being connected together to form a single floating gate, a substrate voltage, a source voltage, a drain voltage, and a control gate voltage being applied on said substrate, said source, said drain and said second doped region, respectively, said method comprising:
performing a program step to let said substrate voltage be grounded or nonzero but close to zero and let said source voltage and said drain voltage be higher than said substrate voltage but much smaller than said control gate voltage; and
performing an erase step to let said source voltage and said drain voltage be higher than said substrate voltage but much smaller than said control gate voltage.
13. A method of operating a nonvolatile memory, said nonvolatile memory comprising an N-well, several first doped regions as a source and a drain and a first conducting gate, and a capacitor structure composed of a second doped region and a second conducting gate on a p-type semiconductor substrate, said first and second conducting gates being connected together to form a single floating gate, a well voltage, a substrate voltage, a source voltage, a drain voltage, and a control gate voltage being applied on said N-well, said substrate, said source, said drain and said second doped region, respectively, said method comprising:
performing a program step to let said substrate voltage be grounded or nonzero but close to zero and let said well voltage and said drain voltage be higher than said source voltage and let said source voltage be higher than said control gate voltage and let said control gate voltage be higher than said substrate voltage; and
performing an erase step to let said well voltage be much larger than said substrate voltage and said control gate voltage be much larger than said well voltage and let said source voltage and said drain voltage be smaller than said substrate voltage.
14. A method of operating a nonvolatile memory, said nonvolatile memory comprising several first doped regions as a source and a drain and a first conducting gate and a capacitor structure composed of a second doped region and a second conducting gate on an n-type semiconductor substrate, said first and second conducting gates being connected together to form a single floating gate, a substrate voltage, a source voltage, a drain voltage, and a control gate voltage being applied on said substrate, said source, said drain and said second doped region, respectively, said method comprising:
performing a program step to let said substrate voltage be grounded or nonzero but close to zero and let said source voltage and said drain voltage be lower than said substrate voltage but much higher than said control gate voltage; and
performing an erase step to let control gate voltage be smaller than said substrate voltage and let said source voltage and said drain voltage be negative but have much smaller magnitudes than that of said control gate voltage.
15. A method of operating a nonvolatile memory, said nonvolatile memory comprising a P-well, several first doped regions as a source and a drain and a first conducting gate and a capacitor structure composed of a second doped region and a second conducting gate on an n-type semiconductor substrate, said first and second conducting gates being connected together to form a single floating gate, a well voltage, a substrate voltage, a source voltage, a drain voltage, and a control gate voltage being applied on said P-well, said substrate, said source, said drain and said second doped region, respectively, said method comprising:
performing a program step to let said substrate voltage be grounded or nonzero but close to zero and let said source voltage be higher than said well voltage and let said drain voltage be higher than said source voltage and let said control gate voltage be higher than said source voltage but smaller than said substrate voltage; and
performing an erase step to let said well voltage be much smaller than said substrate voltage and let said control gate voltage be much smaller than said well voltage and let said source voltage and said drain voltage be higher than said substrate voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A voltage balancing unit for a symmetric monopole high voltage direct current, HVDC, transmission line being arranged for interconnecting a first voltage source converter, VSC, and a second VSC, the transmission line comprising:
a first pole and a second pole, and two pairs of first arresters, a first pair being arranged at a first end of the transmission line and a second pair being arranged at a second end of the transmission line, a first arrester of either pair being connected between the first pole and ground and a second arrester of either pair being connected between the second pole and ground, the first arresters having a first switching impulse protective level, SIPL,
wherein the voltage balancing unit is arranged to perform voltage balancing for a voltage unbalance caused by an earth fault and comprises:
a pair of second arresters having a second SIPL which is less than the first SIPL, and
a switching device configured to:
connect, through being closed after the earth fault has been cleared and in response to determining that the voltage unbalance exists between the first pole and the second pole, a first arrester of the pair of second arresters between the first pole and ground, and a second arrester of the pair of second arresters between the second pole and ground, and
disconnect, in response to determining that the voltage unbalance is cleared, the second arresters.
2. The voltage balancing unit according to claim 1, wherein the pair of second arresters is arranged at either of the ends of the transmission line.
3. A high voltage direct current, HVDC, power transmission unit comprising:
a first voltage source converter, VSC, comprising an alternating current, AC, side and a direct current, DC, side, the AC side of the first VSC being connectable to a first AC network,
a symmetric monopole transmission line being arranged for interconnecting the DC side of the first VSC and a DC side of a second VSC, an AC side of the second VSC being connectable to a second AC network, the transmission line comprising a first pole and a second pole, and
a voltage balancing unit according to claim 2.
4. The voltage balancing unit according to claim 1, wherein the first SIPL is in the range of 1.8 to 2.0 per unit, p.u., and the second SIPL is in the range of 1.15 to 1.20 p.u.
5. A high voltage direct current, HVDC, power transmission unit comprising:
a first voltage source converter, VSC, comprising an alternating current, AC, side and a direct current, DC, side, the AC side of the first VSC being connectable to a first AC network,
a symmetric monopole transmission line being arranged for interconnecting the DC side of the first VSC and a DC side of a second VSC, an AC side of the second VSC being connectable to a second AC network, the transmission line comprising a first pole and a second pole, and
a voltage balancing unit according to claim 4.
6. The voltage balancing unit according to claim 1, wherein the switching device comprises:
a pair of high speed switches, HSSs, a first HSS being connected in series with the first arrester of the pair of second arresters and a second HSS being connected in series with the second arrester of the pair of second arresters, the HSSs being in an open state under normal operation, and
a pair of disconnectors, a first disconnector being connected in series with the first arrester of the pair of second arresters and a second disconnector being connected in series with the second arrester of the pair of second arresters, the disconnectors being in a closed state under normal operation,
wherein the switching means is further configured to:
close, in response to determining that a voltage unbalance exists, the HSSs, and
in response to determining that the voltage unbalance is cleared:
open the disconnectors,
open the HSSs, and
close the disconnectors.
7. A high voltage direct current, HVDC, power transmission unit comprising:
a first voltage source converter, VSC, comprising an alternating current, AC, side and a direct current, DC, side, the AC side of the first VSC being connectable to a first AC network,
a symmetric monopole transmission line being arranged for interconnecting the DC side of the first VSC and a DC side of a second VSC, an AC side of the second VSC being connectable to a second AC network, the transmission line comprising a first pole and a second pole, and
a voltage balancing unit according to claim 6.
8. A high voltage direct current, HVDC, power transmission unit comprising:
a first voltage source converter, VSC, comprising an alternating current, AC, side and a direct current, DC, side, the AC side of the first VSC being connectable to a first AC network,
a symmetric monopole transmission line being arranged for interconnecting the DC side of the first VSC and a DC side of a second VSC, an AC side of the second VSC being connectable to a second AC network, the transmission line comprising a first pole and a second pole, and
a voltage balancing unit according to claim 1.
9. The HVDC power transmission unit according to claim 8, further comprising an AC circuit breaker being arranged for:
disconnecting, in response to determining that a voltage unbalance exists, the first VSC from the first AC network, and
reconnecting, in response to determining that the voltage unbalance is cleared, the first VSC to the first AC network.
10. The HVDC power transmission unit according to claim 8, further comprising a pair of DC circuit breakers being arranged for:
disconnecting, in response to determining that a voltage unbalance exists, the transmission line from the first VSC, and
reconnecting, in response to determining that the voltage unbalance is cleared, the transmission line to the first VSC.
11. A method of voltage balancing in a symmetric monopole high voltage direct current, HVDC, transmission line being arranged for interconnecting a first voltage source converter, VSC, and a second VSC, the transmission line comprising:
a first pole and a second pole, and two pairs of first arresters, a first pair being arranged at a first end of the transmission line and a second pair being arranged at a second end of the transmission line, a first arrester of either pair being connected between the first pole and ground and a second arrester of either pair being connected between the second pole and ground, the first arresters having a first switching impulse protective level, SIPL,
the method being performed for a voltage unbalance caused by an earth fault and comprising the steps of:
providing a pair of second arresters having a second SIPL which is less than the first SIPL,
connecting, through being closed after the earth fault has been cleared and in response to determining that the voltage unbalance exists between the first pole and the second pole, a first arrester of the pair of second arresters between the first pole and ground, and a second arrester of the pair of second arresters between the second pole and ground, and
disconnecting, in response to determining that the voltage unbalance is cleared, the second arresters.
12. The method according to claim 11, wherein the pair of second arresters is connected at either of the ends of the transmission line.
13. The method according to claim 11, wherein the first SIPL is in the range of 1.8 to 2.0 per unit, p.u., and the second SIPL is in the range of 1.15 to 1.20 p.u.
14. The method according to claim 11, further comprising:
providing a pair of high speed switches, HSSs, a first HSS being connected in series with the first arrester of the pair of second arresters and a second HSS being connected in series with the second
arrester of the pair of second arresters, the HSSs being in an open state under normal operation, and
providing a pair of disconnectors, a first disconnector being connected in series with the first arrester of the pair of second arresters and a second disconnector being connected in series with the second arrester of the pair of second arresters, the disconnectors being in a closed state under normal operation,
wherein the step of connecting the second arresters comprises:
closing the HSSs, and
wherein the step of disconnecting the second arresters comprises:
opening the disconnectors,
opening the HSSs, and
closing the disconnectors.
15. The method according to claim 11, wherein the first VSC is connectable to a first AC network, the method further comprising the steps of:
disconnecting, in response to determining that a voltage unbalance exists, the first VSC from the first AC network, and
reconnecting, in response to determining that the voltage unbalance is cleared, the first VSC to the first AC network.
16. The method according to claim 11, further comprising the steps of: disconnecting, in response to determining that a voltage unbalance exists, the transmission line from the first VSC, and
reconnecting, in response to determining that the voltage unbalance is cleared, the transmission line to the first VSC.