1-6. (canceled)
7. A bandpass filter, comprising: a plurality of resonators connected to each other between an input and an output of the filter, and at least two main signal paths leading from the input to the output, the at least two main signal paths having overlapping passbands and being connected via different ones of the resonators to the input and the output.
8. The bandpass filter according to claim 7, in that the two main signal paths have no common resonators.
9. The bandpass filter according to claim 7, in that the at least two main signal paths have overall coupling coefficients with different signs.
10. The bandpass filter according to claim 7, in that at least one cavity resonator is under the resonators.
11. The bandpass filter according to claim 7, in that at least one conduction resonator is under the resonators.
12. The bandpass filter according to claim 7, in that at least one stripline resonator is under the resonators.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing a semiconductor device having recess channels and asymmetrical junctions, the method comprising:
(a) providing a semiconductor substrate comprising laterally located regions for storage node junctions, and a bit line junction, and channel regions disposed laterally between the storage node junctions and the bit line junction;
(b) first implanting p-type ions into the region of the bit line junction and the channel regions to form an impurity region having a depth, and two side parts by using a mask film pattern having a width of one to three times of a feature size;
(c) forming recess channel trenches in the substrate by etching the channel regions to a designated depth, the depth of the recess channel trenches being greater than the depth of the impurity region, so that the recess channel trenches cut out both side parts of the impurity region to confine a width of the impurity region to a reduced width region between the trenches;
(d) forming gate stacks filling the recess channel trenches; and
(e) second implanting n-type ions into the confined impurity region and the regions of the storage node junctions by using the gate stacks as an implanting mask, to form asymmetric junctions such that the bit line junction is formed as a more shallow junction than the storage node junctions due to the confined impurity region.
2. The method according to claim 1, wherein the impurity region has a depth of 50 angstroms (\u212b) to 2,500 \u212b from the surface of the semiconductor substrate.
3. The method according to claim 1, wherein the recess channel trenches have a depth of 50 \u212b to 2,500 \u212b from the surface of the semiconductor substrate.
4. The method according to claim 1, wherein the p-type impurity ions are ones selected from the group consisting of B ions, BF2 ions, and I ions.
5. The method according to claim 1, wherein the width of a mask film pattern for forming the impurity region is in a range of one to three times of the width of a gate mask film pattern forming gates.
6. The method according to claim 1, wherein the n-type impurity ions are selected from the group consisting of P ions and As ions.
7. The method according to claim 1, wherein the n-type impurity ions are implanted such that the n-type impurity ions are disposed on the surface of the impurity region.
8. A method for manufacturing a semiconductor device having recess channels and asymmetrical junctions, the method comprising:
(a) providing a semiconductor substrate comprising laterally located regions for storage node junctions and a bit line junction, and channel regions disposed laterally between the storage node junctions and the bit line junction;
(b) first implanting p-type ions into the region of the bit line junction and the channel regions to form an impurity region;
(c) forming recess channel trenches in the substrate by etching the channel regions to a designated depth so that the recess channel trenches cut out both side parts of the impurity region to confine a width of the impurity region to a reduced width region between the trenches,
(d) forming gate stacks filling the recess channel trenches; and
(e) second implanting n-type ions into the confined impurity region and the regions of the storage node to form junctions to form asymmetric junctions such that the bit line junction is formed as a more shallow junction than the storage node junctions due to the confined impurity region.
9. The method according to claim 8, wherein the impurity region has a depth of 50 angstroms (\u212b) to 2,500 \u212b from the surface of the semiconductor substrate.
10. The method according to claim 8, wherein the recess channel trenches have a depth of 50 \u212b to 2,500 \u212b from the surface of the semiconductor substrate.
11. The method according to claim 8, wherein the p-type impurity ions are ones selected from the group consisting of B ions, BF2 ions, and I ions.
12. The method according to claim 8, wherein the width of a mask film pattern for forming the impurity region is in a range of one to three times of the width of a gate mask film pattern forming gates.
13. The method according to claim 8, wherein the n-type impurity ions are selected from the group consisting of P ions and As ions.
14. The method according to claim 8, wherein the n-type impurity ions are implanted such that the n-type impurity ions are disposed on the surface of the impurity region.