1. A method for preparing an A-B-C2 or A2-(Dx,E1-x)-C4 absorber thin film for photovoltaic cells where 0\u2266x\u22661, A is an element or a mixture of elements selected from group 11, B is an element or a mixture of elements selected from group 13, C is an element or a mixture of elements selected from group 16, D is an element or a mixture of elements selected from group 12 and E is an element or a mixture of elements selected from group 14, said method comprising the following successive steps:
electrodeposition of a thin film of a mixture of oxides andor hydroxides comprising, for an A-B-C2 film, at least one element from group 11 and one element from group 13 or, for an A2-(Dx,E1-x)-C4 film, at least one element from group 11, at least one element from group 12 if x>0, and at least one element from group 14 if x<1,
annealing of the thin film in a reducing atmosphere,
supply of at least one element from group 16 in order to form an A-B-C2 or A2-(Dx,E1-x)-C4 thin film where 0\u2266x\u22661.
2. The method as claimed in claim 1, wherein the electrodeposition is carried out at a temperature of at least 5\xb0 C. and not greater than 95\xb0 C.
3. The method as claimed claim 1, wherein the annealing in reducing atmosphere is carried out at a temperature of at least 300\xb0 C. and not greater than 650\xb0 C.
4. The method as claimed in claim 1, wherein the annealing in reducing atmosphere has a duration of at least 20 seconds and not greater than 15 minutes.
5. The method as claimed in claim 1, wherein, prior to the electrodeposition of the thin film, an aqueous solution is prepared containing a mixture of salts of A and B for an A-B-C2 film or a mixture of salt of A, D andor E for an A2-(Dx,E1-x)-C4 film, in the presence of at least one oxygen donor species.
6. The method as claimed in claim 5, wherein the oxygen donor species consists of a nitrate ion, or of dioxygen, or of hydrogen peroxide or of hypochlorite ions.
7. The method as claimed in claim 1, wherein A is copper or silver or a mixture of copper and silver and C is selenium or sulfur or a mixture of selenium and sulfur.
8. The method as claimed in claim 1, wherein the absorber thin film for photovoltaic cells is the A-B-C2 type and B comprises one or more elements selected from indium, gallium, aluminum or mixtures thereof.
9. The method as claimed in claim 8, wherein the electrodeposition is carried by imposing a current density of between 1 and 30 mA\xb7cm\u22122 or a voltage of at least \u22121.8 V and not greater than \u22120.5 V to an electrode comprising an insulating substrate coated with a film of molybdenum and a saturated HgHg2SO4K2SO4 reference electrode.
10. The method as claimed in claim 8, wherein the atomic ratio of the elements A and B in the electrolyte solution is at least 0.2 and not greater than 1.5.
11. The method as claimed in claim 1, wherein the absorber thin film for photovoltaic cells is the A-B-C2 type and B comprises a mixture of indium and gallium, and wherein the ratio of the indium and gallium concentrations in the electrolyte solution is at least 0.2 and not greater than 1.5.
12. A method for manufacturing a solar cell, comprising the method for preparing an absorber thin film for photovoltaic cells as claimed in claim 1.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A silicon carbide semiconductor device comprising:
an insulation film, and
a silicon carbide layer having a surface covered with said insulation film, said surface including a first region, said first region having a first plane orientation at least partially, said first plane orientation being any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (\u2212303-8) plane, and (3-30-8) plane,
wherein
said surface of said silicon carbide layer further includes a second region, said second region having a second plane orientation differing from said first plane orientation, at least partially,
said second plane orientation is any of the (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.
2. The silicon carbide semiconductor device according to claim 1, wherein
said surface of said silicon carbide layer further includes third to sixth regions, said third to sixth regions, at least partially, having third to sixth plane orientations respectively, said first to sixth plane orientations differing from each other, and
each of said first to sixth plane orientations is any of the (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.
3. The silicon carbide semiconductor device according to claim 1, wherein an interface between said silicon carbide layer and said insulation film has an interface state density less than 5\xd71011 cm\u22122 eV\u22121.
4. The silicon carbide semiconductor device according to claim 1, wherein said silicon carbide semiconductor device has an S value less than or equal to 200 mVdecade.
5. The silicon carbide semiconductor device according to claim 1, further comprising a gate electrode provided on said insulation film.
6. The silicon carbide semiconductor device according to claim 5, wherein said gate electrode constitutes a trench gate structure.
7. The silicon carbide semiconductor device according to claim 5, wherein said gate electrode constitutes a planar gate structure.
8. The silicon carbide semiconductor device according to claim 1, wherein said silicon carbide layer has channel mobility higher than or equal to 70 cm2Vs at room temperature on said surface.
9. The silicon carbide semiconductor device according to claim 8, wherein said silicon carbide layer has an impurity concentration greater than or equal to 1\xd71017 cm\u22123 on said surface.
10. The silicon carbide semiconductor device according to claim 9, wherein said silicon carbide semiconductor device has a threshold value greater than or equal to 4V.
11. The silicon carbide semiconductor device according to claim 1, wherein said silicon carbide layer has channel mobility higher than or equal to 100 cm2Vs at room temperature on said surface.
12. The silicon carbide semiconductor device according to claim 11, wherein said silicon carbide layer has an impurity concentration greater than or equal to 2\xd71016 cm\u22123 on said surface.
13. The silicon carbide semiconductor device according to claim 12, wherein said silicon carbide semiconductor device has a threshold value greater than or equal to 2.5V.
14. A silicon carbide semiconductor device comprising:
an insulation film, and
a silicon carbide layer having a surface covered with said insulation film, said surface including a first region, said first region having a first plane orientation at least partially, an off orientation of said first plane orientation to a {0001} plane being within a range of \xb15\xb0 to a <1-100> direction, an off angle of said first plane orientation to a {03-38} plane in the <1-100> direction being greater than or equal to \u22123\xb0 and less than or equal to 3\xb0, and an inclination of said first plane orientation to a (000-1) plane being less than 90\xb0,
wherein
said surface of said silicon carbide layer further includes a second region, said second region having a second plane orientation differing from said first plane orientation at least partially, an off orientation of said second plane orientation to the {0001} plane being within the range of \xb15\xb0 to the <1-100> direction, an off angle of said second plane orientation to the {03-38} plane in the <1-100> direction being greater than or equal to \u22123\xb0 and less than or equal to 3\xb0, and an inclination of said second plane orientation to the (000-1) plane being less than 90\xb0.
15. The silicon carbide semiconductor device according to claim 14, wherein
said surface of said silicon carbide layer further includes third to sixth regions, said third to sixth regions, at least partially, having third to sixth plane orientations respectively, said first to sixth plane orientations differing from each other, each off orientation of said first to sixth plane orientations to the {0001} plane being within the range of \xb15\xb0 to the <1-100> direction, each off angle of each of said first to sixth plane orientations to the {03-38} plane in the <1-100> direction being greater than or equal to \u22123\xb0 and less than or equal to 3\xb0, and each inclination of each of said first to sixth plane orientations to the (000-1) plane being less than 90\xb0.
16. The silicon carbide semiconductor device according to claim 14, wherein an interface between said silicon carbide layer and said insulation film has an interface state density less than 5\xd71011 cm\u22122 eV\u22121.
17. The silicon carbide semiconductor device according to claim 14, wherein said silicon carbide semiconductor device has an S value less than or equal to 200 mVdecade.
18. The silicon carbide semiconductor device according to claim 14, further comprising a gate electrode provided on said insulation film.
19. The silicon carbide semiconductor device according to claim 18, wherein said gate electrode constitutes a trench gate structure.
20. The silicon carbide semiconductor device according to claim 18, wherein said gate electrode constitutes a planar gate structure.
21. The silicon carbide semiconductor device according to claim 14, wherein said silicon carbide layer has channel mobility higher than or equal to 70 cm2Vs at room temperature on said surface.
22. The silicon carbide semiconductor device according to claim 21, wherein said silicon carbide layer has an impurity concentration greater than or equal to 1\xd71017 cm\u22123 on said surface.
23. The silicon carbide semiconductor device according to claim 22, wherein said silicon carbide semiconductor device has a threshold value greater than or equal to 4V.
24. The silicon carbide semiconductor device according to claim 14, wherein said silicon carbide layer has channel mobility higher than or equal to 100 cm2Vs at room temperature on said surface.
25. The silicon carbide semiconductor device according to claim 24, wherein said silicon carbide layer has an impurity concentration greater than or equal to 2\xd71016 cm\u22123 on said surface.
26. The silicon carbide semiconductor device according to claim 25, wherein said silicon carbide semiconductor device has a threshold value greater than or equal to 2.5V.