1. A scheduler that causes a given core in a multi-core processor to execute processing comprising:
determining if a priority level of a process that is to be executed and among a group of processes assigned to and executed by cores of the multi-core processor is greater than or equal to a threshold;
saving to a cache memory of each core that executes among processes to be executed, a high-priority process for which the priority level has been determined to be greater than or equal to the threshold, data that is accessed by the high-priority process upon execution;
saving to a memory area different from the cache memory and to which access is slower than access to the cache memory, data that is accessed by a low-priority process for which the priority level has been determined to not be greater than or equal to the threshold; and
saving the data saved in the memory area, to a cache memory of a requesting core in the multi-core processor, when the requesting core issues an access request for the data saved in the memory area.
2. The scheduler according to claim 1, wherein
the saving to the cache memory includes saving to a cache memory of each core that executes the low-priority process, the data that is accessed by the low-priority process upon execution, when the high-priority process is not present among processes to be executed.
3. The scheduler according to claim 1, wherein
the saving to the cache memory includes prohibiting until execution of the high-priority process is completed, overwriting with different data, the data that is saved to the cache memory of each core executing the high-priority process and that is accessed by the high-priority process upon execution.
4. The scheduler according to claim 1, the processing further comprising identifying a capacity of a rewritable area in a cache memory of each core of the multi-core processor when the determining is performed, wherein
the saving to the cache memory includes saving to the cache memory in descending order of updating frequency and when an identified capacity of a rewritable area is smaller than a volume of the data accessed by the high-priority process upon execution, the data accessed by the high-priority process and of a volume that can be stored in the cache memory, and
the saving to the memory area includes saving to the memory area, the data that cannot be saved to the cache memory at the saving to the cache memory.
5. The scheduler according to claim 4, wherein
the saving to the cache memory includes saving to the cache memory in descending order of updating frequency, after the saving of the data accessed by the high-priority process is completed and when an identified capacity of a rewritable area is larger than a volume of the data accessed by the high-priority process upon execution, the data accessed by the low-priority process upon execution and of a volume that can be saved in the cache memory.
6. The scheduler according to claim 1, wherein
the memory area is among a plurality of memory areas respectively differing in access speed,
the saving to the memory area includes saving to the memory areas in descending order of access speed, the data accessed by the low-priority process upon execution and of a volume that can be stored to the respective memory area.
7. The scheduler according to claim 1, the processing further comprising:
extracting from the processes to be executed, processes that access common data upon execution; and
assigning the extracted processes to a single core among the cores of the multi-core processor.
8. The scheduler according to claim 7, wherein the assigning includes assigning to the single core, processes having an identical priority level, among the extracted processes.
9. A multi-core processor system comprising a given core configured to:
determine if a priority level of a process that is to be executed and among a group of processes assigned to and executed by cores of the multi-core processor is greater than or equal to a threshold;
save to a cache memory of each core that executes among processes to be executed, a high-priority process for which the priority level has been determined to be greater than or equal to the threshold, data that is accessed by the high-priority process upon execution;
save to a memory area different from the cache memory and to which access is slower than access to the cache memory, data that is accessed by a low-priority process for which the priority level has been determined to not be greater than or equal to the threshold; and
save the data saved in the memory area, to a cache memory of a requesting core in the multi-core processor, when the requesting core issues an access request for the data saved in the memory area.
10. A scheduling method executed by a given core in a multi-core processor, the scheduling method comprising:
determine if a priority level of a process that is to be executed and among a group of processes assigned to and executed by cores of the multi-core processor is greater than or equal to a threshold;
save to a cache memory of each core that executes among processes to be executed, a high-priority process for which the priority level has been determined to be greater than or equal to the threshold, data that is accessed by the high-priority process upon execution;
save to a memory area different from the cache memory and to which access is slower than access to the cache memory, data that is accessed by a low-priority process for which the priority level has been determined to not be greater than or equal to the threshold; and
save the data saved in the memory area, to a cache memory of a requesting core in the multi-core processor, when the requesting core issues an access request for the data saved in the memory area.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electric parking brake mechanism, for pressing a friction member to a braked member via a force transmission converting mechanism for converting a rotational movement of an electric motor to a linear movement, comprising:
an input shaft connected to a side of the electric motor;
an output shaft connected to a side of the brake mechanism for pressing the friction member to the braked member, and
a cam mechanism interposed between the input shaft and the output shaft,
wherein the cam mechanism includes a plurality of cam members each having a cam face a radius of which is gradually increased relative to a rotational center,
the parking brake mechanism having a configuration wherein the input shaft is not driven by the electric motor, the output shaft is driven by a force from the friction member, and all of the plurality of cam members have been operated to move to sides of large diameters to hamper rotation of the output shaft.
2. An electric parking brake mechanism, for pressing a friction member to a braked member via a force transmission converting mechanism for converting a rotational movement of an electric motor to a linear movement, comprising:
an input shaft connected to a side of the electric motor;
an output shaft connected to a side of the brake mechanism for pressing the friction member to the braked member, and
a cam mechanism interposed between the input shaft and the output shaft,
wherein the cam mechanism includes:
a rotating member contained in a nonrotating member having a circular-shaped inner face, rotatable along with the output shaft;
a second cam member slidable in a radius direction in the rotating member, having an outer face a diameter of which is increased to one side in a peripheral direction,
a first cam member disposed on an inner side of the second cam member, having an outer face a diameter of which is increased to other side in the peripheral direction, rotatable along with the input shaft, and
a locking member arranged between the second cam member and the nonrotating member.
3. The electric parking brake mechanism according to claim 2, wherein the locking member is urged by an elastic member to a side of a large diameter of the second cam member.
4. The electric parking brake mechanism according to claim 1, wherein the output shaft is arranged to penetrate the input shaft.
5. The electric parking brake mechanism according to claim 2, wherein the output shaft is arranged to penetrate the input shaft.
6. The electric parking brake mechanism according to claim 3, wherein the output shaft is arranged to penetrate the input shaft.