1. A photoelectric conversion device comprising:
a light-absorbing layer including a compound semiconductor capable of photoelectric conversion, the compound semiconductor containing a group Ib element including Cu, a group IIIb element and a group VIb element; and
a semiconductor layer on one surface-side of the light-absorbing layer, the semiconductor layer having a plane orientation different from that of the light-absorbing layer, the semiconductor layer containing a group Ib element including Cu, at least one element selected from Cd, Zn and In, and a group VIb element,
wherein the photoelectric conversion device includes
a region in which Cu content decreases from the light-absorbing layer to the semiconductor layer across a junction interface; and
a plurality of Cu-deficient portions which are present at mutual intervals and a remaining portion other than the Cu-deficient portions are present in the one surface-side of the light-absorbing layer, the Cu-deficient portions including a higher content of the at least one element selected from Cd, Zn, and In than the remaining portion and a lower content of Cu than the remaining portion.
2. The photoelectric conversion device according to claim 1, wherein the group VIb element included in the light-absorbing layer includes Se and the group VIb element included in the semiconductor layer includes S, wherein S content increases from the light-absorbing layer to the semiconductor layer across the junction interface.
3. The photoelectric conversion device according to claim 1, wherein the light-absorbing layer has a plane orientation of (112) and the semiconductor layer has a plane orientation of (111).
4. The photoelectric conversion device according to claim 1, wherein the region extends 10 nm or more from the junction interface in a direction perpendicular to the junction interface.
5. The photoelectric conversion device according to claim 1, wherein the Cu-deficient portion has an average width in a direction parallel to the junction interface of 10 to 300 nm in a cross-sectional view of the light-absorbing layer taken in its thickness direction.
6. The photoelectric conversion device according to claim 1, wherein the Cu-deficient portion has an average depth in a direction perpendicular to the junction interface of 10 nm or more in a cross-sectional view of the light-absorbing layer taken in its thickness direction.
7. The photoelectric conversion device according to claim 1, wherein the Cu-deficient portion has an occupancy ratio in the junction interface of 10% or more in a cross-sectional view of the light-absorbing layer taken in its thickness direction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming an insulated gate bipolar transistor (IGBT) device, comprising:
forming a p-type drift layer;
forming an n-type well in the p-type drift layer;
epitaxially growing a p-type channel adjustment layer on the p-type drift layer and on the n-type well;
implanting p-type dopant ions to form a p-type emitter region extending through the channel adjustment layer and into the n-type well at a surface of the drift layer, the p-type emitter region at least partially defining a channel region in the n-type well adjacent the p-type emitter region;
implanting n-type dopant ions to form an n-type connector region extending through the channel adjustment layer and into the n-type well at a surface of the drift layer;
forming a gate oxide layer on the channel region; and
forming a gate on the gate oxide layer.
2. The method of claim 1, further comprising annealing the implanted ions.
3. The method of claim 2, further comprising:
forming a graphite coating on the channel adjustment layer, wherein annealing the implanted ions comprises annealing the channel adjustment layer and the graphite coating; and
removing the graphite coating after annealing the implanted ions.
4. The method of claim 3, further comprising crystallizing the graphite coating before annealing the implanted ions.
5. The method of claim 3, wherein annealing the implanted ions comprises annealing the implanted ions at a temperature greater than 1700\xb0 C.
6. The method of claim 3, wherein annealing the implanted ions comprises annealing the implanted ions at a temperature greater than 1800\xb0 C.
7. The method of claim 1, wherein forming the gate oxide layer comprises forming the gate oxide layer in dry O2, the method further comprising annealing the gate oxide layer in wet O2.
8. The method of claim 7, wherein forming the gate oxide layer comprises forming the gate oxide layer in dry O2 at a temperature less than or equal to about 1200\xb0 C.
9. The method of claim 7, further comprising annealing the gate oxide layer in an inert atmosphere at a temperature less than or equal to about 1200\xb0 C. after forming the gate oxide layer and before annealing the gate oxide layer in wet O2.
10. The method of claim 7, wherein annealing the gate oxide layer in wet O2 comprises annealing the gate oxide layer in wet O2 at a temperature less than or equal to about 950\xb0 C.
11. The method of claim 10, wherein annealing the gate oxide layer in wet O2 comprises annealing the gate oxide layer in wet O2 for at least one hour.
12. The method of claim 7, wherein annealing the oxide layer in wet O2 comprises generating pyrogenic steam in a pyrogenic chamber, supplying the pyrogenic steam to an anneal chamber, and annealing the oxide layer in the anneal chamber.
13. The method of claim 12, wherein generating pyrogenic steam comprises heating the pyrogenic chamber, supplying hydrogen and oxygen gas to the pyrogenic chamber, and combusting the hydrogen gas and the oxygen gas to form the pyrogenic steam, wherein the hydrogen gas and the oxygen gas are supplied to the pyrogenic chamber at a molecular ratio of hydrogen to oxygen of about 1.8 or more.
14. The method of claim 1, further comprising implanting p-type dopant ions into the drift layer to form a HET region adjacent to the n-type well, and wherein the p-type emitter region is spaced apart from the NET region and defines a channel region between the p-type emitter region and the JFBT region.
15. The method of claim 1, wherein the channel adjustment layer is formed to have a thickness of about 0.1 \u03bcm to about 0.5 \u03bcm, and wherein the channel adjustment layer has a net acceptor concentration of about 1\xd71016 cm\u22123 to about 5\xd71018 cm\u22123.
16. The method of claim 1, wherein the drift layer comprises an epitaxial silicon carbide layer.
17. The method of claim 1, where the forming the p-type drift layer comprises forming the p-type drift layer on an n-type substrate.
18. The method of claim 17, wherein the substrate comprises silicon carbide.
19. The method of claim 1, wherein a distance from a bottom of the p-type emitter region to a bottom of the n-type well region is equal to or greater than about 0.45 \u03bcm.
20. A method of forming an insulated gate bipolar transistor (IGBT) device, comprising:
forming a drift layer of a first conductivity type;
forming a well of a second conductivity type in the drift layer;
forming a JFET region with first conductivity type dopant ions in the drift layer;
forming a channel adjustment layer of the first conductivity type on the HET region and the well;
implanting first conductivity type dopant ions to form an emitter region of the first conductivity type extending through the channel adjustment layer and into the well, wherein the emitter region is spaced apart from the NET region by the well;
implanting second conductivity type dopant ions to form a connector region of the second conductivity type adjacent the emitter region;
forming a gate oxide layer on the channel region; and
forming a gate on the gate oxide layer.
21. The method of claim 20, wherein forming the HET region comprises epitaxially growing the JFET region with additional first conductivity type dopant ions on the drift layer.
22. The method of claim 20, wherein forming the HET region comprises forming the JFET region with a dopant concentration of about 1\xd71016 cm\u22123.
23. The method of claim 20, wherein forming the JFET region comprises implanting aluminum in the drift lay adjacent the well.
24. The method of claim 20, further comprising:
forming a graphite coating on the channel adjustment layer;
annealing the implanted ions in the channel adjustment layer;
annealing the graphite coating; and
removing the graphite coating after annealing the implanted ions.