1. A receiving apparatus comprising:
A receiver which, in operation, receives a signal including downlink control information mapped to a first search space or a second search space, the first search space including one or a plurality of first PDCCH candidates for each of a plurality of aggregation levels, the second search space including one or a plurality of second PDCCH candidates for each of the plurality of aggregation levels and further including at least one other second PDCCH candidate for an aggregation level higher than any one of the plurality of aggregation levels, each of the first and the second PDCCH candidate being composed of a control channel element (CCE) or a plurality of aggregated CCEs of its corresponding aggregation level; and
a monitor which, in operation, monitors the one or the plurality of first PDCCH candidates included in the first search space or the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space and to acquire downlink control information for the receiving apparatus.
2. The receiving apparatus according to claim 1, wherein
the one or the plurality of first PDCCH candidates included in the first search space are allocated for localized transmission; and
the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space are allocated for distributed transmission.
3. The receiving apparatus according to claim 1, wherein for each of the plurality of aggregation levels, a frequency position of the one or the plurality of first PDCCH candidates included in the first search space does not overlap with a frequency position of any one of the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space.
4. The receiving apparatus according to claim 1, wherein the plurality of first PDCCH candidates included in the first search space and the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space are allocated for distributed transmission.
5. The receiving apparatus according to claim 1, wherein at least one of the first search space and the second search space defines a smaller number of PDCCH candidates as an aggregation level gets higher.
6. The receiving apparatus according to claim 1, wherein both of the first search space and the second search space are UE-specific search spaces.
7. A receiving method comprising:
receiving a signal including downlink control information mapped to a first search space or a second search space, the first search space including one or a plurality of first PDCCH candidates for each of a plurality of aggregation levels, the second search space including one or a plurality of second PDCCH candidates for each of the plurality of aggregation levels and further including at least one other second PDCCH candidate for an aggregation level higher than any one of the plurality of aggregation levels, each of the first and the second PDCCH candidate being composed of a control channel element (CCE) or a plurality of aggregated CCEs of its corresponding aggregation level; and
monitoring the one or the plurality of first PDCCH candidates included in the first search space or the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space and acquiring downlink control information for a receiving apparatus.
8. The receiving method according to claim 7, wherein
the one or the plurality of first PDCCH candidates included in the first search space are allocated for localized transmission; and
the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space are allocated for distributed transmission.
9. The receiving method according to claim 7, wherein
for each of the plurality of aggregation levels, a frequency position of the one or the plurality of first PDCCH candidates included in the first search space does not overlap with a frequency position of any one of the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space.
10. The receiving method according to claim 7, wherein the plurality of first PDCCH candidates included in the first search space and the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space are allocated for distributed transmission.
11. The receiving method according to claim 7, wherein at least one of the first search space and the second search space defines a smaller number of PDCCH candidates an aggregation level gets higher.
12. The receiving method according to claim 7, wherein both of the first search space and the second search space are UE-specific search spaces.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of making a plurality of conductive memory devices comprising:
forming a bottom electrode layer;
forming a multi-resistive state element layer;
forming a top electrode layer;
forming a hard mask layer;
patterning the hard mask layer and the top electrode layer such that the patterned top electrode and hard mask have a first cross sectional area;
forming a dielectric material layer;
etching the dielectric material to create a sidewall spacer; and
etching the multi-resistive state element layer and the bottom electrode layer using the hard mask such that the etched bottom electrode and multi-resistive state element have a second cross sectional area that is larger than the first cross sectional area.
2. A method of making a plurality of conductive memory devices, each conductive memory device operable to be reversibly placed in multiple resistive states, the method comprising:
sputtering a bottom electrode layer;
sputtering a multi-resistive state element layer;
sputtering a top electrode layer;
depositing a hard mask layer;
photo lithographically patterning the hard mask layer and the top electrode layer such that the patterned top electrode and hard mask have a first cross sectional area;
depositing a dielectric material;
etching the dielectric anisotropically to create a sidewall spacer at the edges of the top electrode; and
etching the multi-resistive state element layer and the bottom electrode layer using the hard mask such that the etched bottom electrode and multi-resistive state element have a second cross sectional area that is larger than the first cross sectional area.
3. The method of making a plurality of conductive memory devices of claim 2 wherein the multi-resistive state element layer and the top electrode layer have an interface that is modified.
4. The method of making a plurality of conductive memory devices of claim 3 wherein modification of the interface is performed by either ion implantation, in situ argon plasma treatment, in situ oxygen plasma treatment, in situ annealing in argon or in situ annealing in oxygen.
5. The method of making a plurality of conductive memory devices of claim 2 further comprising:
wet etching the multi-resistive state element layer
wherein the wet etching is performed after the etching of the multi-resistive state element layer, the etching of the multi-resistive state element layer forming multi-resistive state element sides; and
wherein the wet etching of the multi-resistive state element removes a thickness of 50-150 \u212b, thereby forming an undercut from the multi-resistive state element sides.
6. The method of making a plurality of conductive memory devices of claim 2 wherein at least one etching is performed via high temperature reactive ion etching.