1-36. (canceled)
37. A semiconductor device comprising:
a first pixel over a substrate, and comprising:
a first TFT comprising:
a first portion of a first semiconductor layer comprising a first channel region, a pair of first LDD regions in contact with the first channel region, and first source and drain regions on the outside of the pair of first LDD regions;
a first gate insulating film over the first portion of the first semiconductor layer; and
a first gate electrode over the first gate insulating film, a capacitor comprising:
a first layer comprising a second portion of the first semiconductor layer;
a second layer over the first layer, and comprising a same layer as the first gate insulating film; and
a third layer over the second layer, and comprising a same layer as the first gate electrode,
an insulating film comprising silicon nitride, and over and in contact with the first gate electrode and the first gate insulating film,
wherein a third portion of the first semiconductor layer extends to a second pixel, and
wherein a thickness of the first gate insulating film over the first channel region is thicker than a thickness of the first gate insulating film over each of the first source and drain regions,
a driver circuit over the substrate, and comprising an n-channel TFT and a p-channel TFT,
wherein each of the n-channel TFT and the p-channel TFT comprises:
a second semiconductor layer comprising a second channel region, a pair of second LDD regions in contact with the second channel region, and second source and drain regions disposed on the outside of the pair of second LDD regions;
a second gate insulating film provided over the second semiconductor layer; and
a second gate electrode provided over the second gate insulating film, and
wherein a thickness of the second gate insulating film over the second channel region is thicker than a thickness of the second gate insulating film over each of the second source and drain regions.
38. A semiconductor device according to claim 37, wherein each of the first gate electrode, the second gate electrode and the third layer has a tapered portion.
39. A semiconductor device according to claim 38, wherein an angle of the tapered portion is between 5\xb0 and 45\xb0.
40. A semiconductor device according to claim 37, wherein each of the first gate electrode and the second gate electrode comprises a heat resistant conductive material and a gate wiring that is electrically connected to the first gate electrode comprises a low resistivity conductive material.
41. A semiconductor device according to claim 40, wherein the heat resistant conductive material is selected from a group consisting of an element selected from tantalum, titanium, or tungsten.
42. A semiconductor device according to claim 37, wherein each of the first gate insulating film and the second gate insulating film comprises an insulating film containing silicon.
43. A semiconductor device according to claim 37, wherein a concentration of an impurity element in each of the pair of first LDD regions are set to become higher as the distance from the first channel region increases.
44. A semiconductor device according to claim 37, wherein the semiconductor device is applied to an electronic appliance selected from a group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, an electronic game machine, and a projector.
45. A semiconductor device according to claim 37, wherein the first TFT has a multi gate structure.
46. A semiconductor device according to claim 43, wherein the second portion of the first semiconductor layer contains the impurity element.
47. A semiconductor device according to claim 37, wherein the first pixel and the second pixel are electrically connected to a same source wiring.
48. A semiconductor device according to claim 47, wherein a fourth portion of the first semiconductor layer is connected to the source wiring.
49. A semiconductor device comprising:
a first pixel over a substrate, and comprising:
a first TFT comprising:
a first portion of a first semiconductor layer comprising a first channel region, a pair of first LDD regions in contact with the first channel region, and first source and drain regions on the outside of the pair of first LDD regions;
a first gate insulating film over the first portion of the first semiconductor layer; and
a first gate electrode over the first gate insulating film, a capacitor comprising:
a first layer comprising a second portion of the first semiconductor layer;
a second layer over the first layer, and comprising a same layer as the first gate insulating film; and
a third layer over the second layer, and comprising a same layer as the first gate electrode,
an insulating film comprising silicon nitride, and over and in contact with the first gate electrode and the first gate insulating film,
wherein a third portion of the first semiconductor layer extends to a second pixel, and
wherein a thickness of the first gate insulating film over the first channel region is thicker than a thickness of the first gate insulating film over each of the first source and drain regions,
a driver circuit over the substrate, and comprising a second TFT,
wherein the second TFT comprises:
a second semiconductor layer comprising a second channel region, a pair of second LDD regions in contact with the second channel region, and second source and drain regions disposed on the outside of the pair of second LDD regions;
a second gate insulating film provided over the second semiconductor layer; and
a second gate electrode provided over the second gate insulating film, and
wherein a thickness of the second gate insulating film over the second channel region is thicker than a thickness of the second gate insulating film over each of the second source and drain regions.
50. A semiconductor device according to claim 49, wherein each of the first gate electrode, the second gate electrode and the third layer has a tapered portion.
51. A semiconductor device according to claim 50, wherein an angle of the tapered portion is between 5\xb0 and 45\xb0.
52. A semiconductor device according to claim 49, wherein each of the first gate electrode and the second gate electrode comprises a heat resistant conductive material and a gate wiring that is electrically connected to the first gate electrode comprises a low resistivity conductive material.
53. A semiconductor device according to claim 52, wherein the heat resistant conductive material is selected from a group consisting of an element selected from tantalum, titanium, or tungsten.
54. A semiconductor device according to claim 49, wherein each of the first gate insulating film and the second gate insulating film comprises an insulating film containing silicon.
55. A semiconductor device according to claim 49, wherein a concentration of an impurity element in each of the pair of first LDD regions are set to become higher as the distance from the first channel region increases.
56. A semiconductor device according to claim 49, wherein the semiconductor device is applied to an electronic appliance selected from a group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, an electronic game machine, and a projector.
57. A semiconductor device according to claim 49, wherein the first TFT has a multi gate structure.
58. A semiconductor device according to claim 55, wherein the second portion of the first semiconductor layer contains the impurity element.
59. A semiconductor device according to claim 49, wherein the first pixel and the second pixel are electrically connected to a same source wiring.
60. A semiconductor device according to claim 59, wherein a fourth portion of the first semiconductor layer is connected to the source wiring.
61. A semiconductor device comprising:
a first pixel over a substrate, and comprising:
a first TFT comprising:
a first portion of a first semiconductor layer comprising a first channel region, a pair of first LDD regions in contact with the first channel region, and first source and drain regions on the outside of the pair of first LDD regions;
a first gate insulating film over the first portion of the first semiconductor layer; and
a first gate electrode over the first gate insulating film, a capacitor comprising:
a first layer comprising a second portion of the first semiconductor layer;
a second layer over the first layer, and comprising a same layer as the first gate insulating film; and
a third layer over the second layer, and comprising a same layer as the first gate electrode,
an insulating film comprising silicon nitride, and over and in contact with the first gate electrode and the first gate insulating film; and
a first pixel electrode over the insulating film, and electrically connected to the first TFT,
wherein a third portion of the first semiconductor layer is overlapped with a second pixel electrode in a second pixel, and
wherein a thickness of the first gate insulating film over the first channel region is thicker than a thickness of the first gate insulating film over each of the first source and drain regions.
62. A semiconductor device according to claim 61, wherein each of the first gate electrode and the third layer has a tapered portion.
63. A semiconductor device according to claim 62, wherein an angle of the tapered portion is between 5\xb0 and 45\xb0.
64. A semiconductor device according to claim 61, wherein the first gate electrode comprises a heat resistant conductive material and a gate wiring that is electrically connected to the first gate electrode comprises a low resistivity conductive material.
65. A semiconductor device according to claim 64, wherein the heat resistant conductive material is selected from a group consisting of an element selected from tantalum, titanium, or tungsten.
66. A semiconductor device according to claim 61, wherein the first gate insulating film comprises an insulating film containing silicon.
67. A semiconductor device according to claim 61, wherein a concentration of an impurity element in each of the pair of first LDD regions are set to become higher as the distance from the first channel region increases.
68. A semiconductor device according to claim 61, wherein the semiconductor device is applied to an electronic appliance selected from a group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, an electronic game machine, and a projector.
69. A semiconductor device according to claim 61, wherein the first TFT has a multi gate structure.
70. A semiconductor device according to claim 67, wherein the second portion of the first semiconductor layer contains the impurity element.
71. A semiconductor device according to claim 61, wherein the first pixel and the second pixel are electrically connected to a same source wiring.
72. A semiconductor device according to claim 71, wherein a fourth portion of the first semiconductor layer is connected to the source wiring.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A heater controller system for a fusing apparatus configured for fusing marking material to a substrate in a printing system, said heater controller system comprising:
a heating element having at least two sections;
a power source for supplying power to said heating element; and
at least one switch configured to selectively control at least two bidirectional switches for selectively providing current supplied by the power source to at least one of the at least two sections during operation of said heater controller system in one of at least two modes of operation, each of the at least two modes of operation corresponds to a particular size of said substrate.
2. A heater controller system according to claim 1, wherein the at least one switch is at least one diode and the at least bidirectional switches are at least two triacs.
3. A heater controller system according to claim 1, wherein the power source is an AC power source.
4. A heater controller system according to claim 1, wherein the size of the substrate is selected from the group consisting of A5 short edge feed, 11\u2033 short edge feed, and 11\u2033 long edge feed.
5. A heater controller system according to claim 4, wherein in a first mode of operation of the at least two modes of operation the size of the substrate is A5 short edge feed, in a second mode of operation of the at least two modes of operation the size of the substrate is 11\u2033 short edge feed, and in a third mode of operation of the at least two modes of operation the size of the substrate is 11\u2033 long edge feed.
6. A heater controller system according to claim 1, wherein the printing system is a xerographic printing system.
7. A heater controller system for a fusing apparatus configured for fusing marking material to a substrate in a printing system, said heater controller system comprising:
a first heating element having at least two sections;
a second heating element having at least two sections;
a power source for supplying power to the first and second heating elements; and
at least two switches configured to selectively control at least two bidirectional switches for selectively providing current supplied by the power source to at least one section of the at least two sections of at least one of the first and second heating elements during operation of said heater controller system in one of at least two modes of operation, each of the at least two modes of operation corresponds to a particular size of said substrate.
8. A heater controller system according to claim 7, wherein the at least two switches are at least two diodes and the at least two bidirectional switches are at least two triacs.
9. A heater controller system according to claim 7, wherein the power source is an AC power source.
10. A heater controller system according to claim 7, wherein the size of the substrate is selected from the group consisting of A5 short edge feed, A5 long edge feed, 11\u2033 short edge feed, and 11\u2033 long edge feed.
11. A heater controller system according to claim 10, wherein in a first mode of operation of the at least two modes of operation the size of the substrate is A5 short edge feed, in a second mode of operation of the at least two modes of operation the size of the substrate is 11\u2033 short edge feed, in a third mode of operation of the at least two modes of operation the size of the substrate is 11\u2033 long edge feed, and in a fourth mode of operation of the at least two modes of operation the size of the substrate is A4 long edge feed.
12. A heater controller system according to claim 7, wherein the printing system is a xerographic printing system.
13. A xerographic printing system comprising:
a fusing apparatus configured for fusing marking material to a substrate; and
a heater controller system comprising:
a heating element having at least two sections;
a power source for supplying power to said heating element; and
at least one switch configured to selectively control at least two bidirectional switches for selectively providing current supplied by the power source to at least one of the at least two sections during operation of said heater controller system in one of at least two modes of operation, each of the at least two modes of operation corresponds to a particular size of said substrate provided to said fusing apparatus.
14. A xerographic printing system according to claim 13, wherein the at least one switch is at least one diode and the at least bidirectional switches are at least two triacs.
15. A xerographic printing system according to claim 13, wherein the power source is an AC power source.
16. A xerographic printing system according to claim 13, wherein the size of the substrate is selected from the group consisting of A5 short edge feed, 11\u2033 short edge feed, and 11\u2033 long edge feed.
17. A xerographic printing system according to claim 16, wherein in a first mode of operation of the at least two modes of operation the size of the substrate is A5 short edge feed, in a second mode of operation of the at least two modes of operation the size of the substrate is 11\u2033 short edge feed, and in a third mode of operation of the at least two modes of operation the size of the substrate is 11\u2033 long edge feed.
18. A xerographic printing system comprising:
a fusing apparatus configured for fusing marking material to a substrate; and
a heater controller system comprising:
a first heating element having at least two sections;
a second heating element having at least two sections;
a power source for supplying power to the first and second heating elements; and
at least two switches configured to selectively control at least two bidirectional switches for selectively providing current supplied by the power source to at least one section of the at least two sections of at least one of the first and second heating elements during operation of said heater controller system in one of at least two modes of operation, each of the at least two modes of operation corresponds to a particular size of said substrate provided to said fusing apparatus.
19. A xerographic printing system according to claim 18, wherein the at least two switches are at least two diodes and the at least two bidirectional switches are at least two triacs.
20. A xerographic printing system according to claim 18, wherein the power source is an AC power source.
21. A xerographic printing system according to claim 18, wherein the size of the substrate is selected from the group consisting of A5 short edge feed, A5 long edge feed, 11\u2033 short edge feed, and 11\u2033 long edge feed.
22. A xerographic printing system according to claim 21, wherein in a first mode of operation of the at least two modes of operation the size of the substrate is A5 short edge feed, in a second mode of operation of the at least two modes of operation the size of the substrate is 11\u2033 short edge feed, in a third mode of operation of the at least two modes of operation the size of the substrate is 11\u2033 long edge feed, and in a fourth mode of operation of the at least two modes of operation the size of the substrate is A4 long edge feed.