1. A high voltage switch, comprising:
an input configured to receive an input signal;
an output configured to provide an output signal;
at least a first and a second diode, configured in antiseries between said input and output;
a common node of the at least first and second diodes configured to receive a triggering signal to cause the first and second diodes to form a conduction path between the input and the output of the switch; and
a triggering block coupled to said common node and configured to provide the triggering signal to said common node to store charges in said first and second diodes and start the conduction path through said first and second diodes.
2. The high voltage switch according to claim 1 wherein said triggering block is coupled between a voltage supply reference and said common node and has a control input configured to receive a starting signal, the starting signal being an ONOFF short pulse.
3. The high voltage switch according to claim 2 wherein said voltage supply reference is a low voltage supply reference.
4. The high voltage switch according to claim 2 wherein said triggering block comprises a DMOS transistor, a third diode and a resistor, coupled in series between said voltage supply reference and said common node, said DMOS transistor also having a control coupling coupled to said control input.
5. The high voltage switch according to claim 4 wherein said starting signal provides said DMOS transistor with a short pulse, which, through said resistor, forces a triggering current in said second diode, switching said high voltage switch on.
6. The high voltage switch according to claim 5 wherein said starting signal provides junction charges of said first and second diodes in an amount sufficient to switching said diodes on before said input signal is applied to said input to trigger said high voltage switch.
7. The high voltage switch according to claim 4 wherein said DMOS transistor has an intrinsic body-source diode being in antiseries with said third diode.
8. The high voltage switch according to claim 7 wherein said DMOS transistor is a P-channel high voltage transistor.
9. The high voltage switch according to claim 7 wherein said intrinsic body-source diode of said DMOS transistor and said third diode have anodes coupled together.
10. The high voltage switch according to claim 1 wherein said first and second diodes have anodes coupled together.
11. The high voltage switch according to claim 1 wherein said output is configured to couple to a piezoelectric transducer as a load and said input is configured to couple to a generator of a pulsed HV trapezoidal waveform.
12. A system, comprising:
a switch including:
a first diode configured to couple to an output;
a second diode coupled in antiseries with the first diode and configured to couple to an input; and
a common node of the first and second diodes configured to receive a triggering signal; and
a triggering block coupled to the common node and configured to selectively generate the triggering signal, wherein the switch is configured to form a conductive path between the input and the output through the first and second diodes in response to the triggering signal.
13. The system of claim 12 wherein the triggering block is coupled between a voltage supply reference and the common node and configured to receive a control signal and to selectively generate the triggering signal based on the control signal.
14. The system of claim 13 wherein the control signal is a pulse signal.
15. The system of claim 14 wherein the triggering block is configured to respond to the pulse signal by forcing a triggering current in the second diode.
16. The system of claim 13 wherein the triggering block comprises a DMOS transistor, a third diode and a resistor, coupled in series between the voltage supply reference and the common node, said DMOS transistor comprising a control coupling configured to receive the control signal.
17. The system of claim 16 wherein the DMOS transistor comprises an intrinsic body-source diode coupled in antiseries with the third diode.
18. The system of claim 16 wherein the DMOS transistor is a P-channel high voltage transistor.
19. The system of claim 16, further comprising:
a piezoelectric transducer coupled to the output of the switch; and
a generator coupled to the input of the switch and configured to generate a pulsed HV trapezoidal waveform.
20. The system of claim 16, further comprising:
a load controller coupled to the triggering block and configured to generate the control signal.
21. The system of claim 12 wherein the first and second diodes comprise first and second transistors in a diode configuration.
22. A method, comprising:
coupling first and second diodes together in anti-series between a high-voltage signal source and a load;
generating a triggering signal in a triggering block; and
applying the triggering signal to a common node of the first and second diodes, the triggering signal creating an overvoltage condition of one of the first and second diodes to form a conductive path through the first and second diodes and between the high-voltage signal source and the load.
23. The method of claim 22 comprising coupling the triggering block between a voltage supply reference and the common node.
24. The method of claim 23, further comprising receiving a control signal wherein the generating the triggering signal comprises generating the triggering signal based on the control signal.
25. The method of claim 24 wherein the triggering block comprises a DMOS transistor, a third diode and a resistor, coupled in series between the voltage supply reference and the common node, said DMOS transistor comprising a control coupling configured to receive the control signal.
26. The method of claim 24, further comprising generating the control signal.
27. The method of claim 26 wherein generating the control signal comprises generating a pulse signal.
28. A system, comprising:
means for generating a high-voltage signal;
means for receiving the high-voltage signal; and
means for selectively creating a conductive path through first and second diodes coupled together in anti-series between the means for generating and the means for receiving.
29. The system of claim 28 wherein the means for generating comprises a high-voltage pulse generator.
30. The system of claim 28 wherein the means for receiving comprises a piezoelectric transducer.
31. The system of claim 28 wherein the means for selectively creating comprises a triggering block.
32. The system of claim 28, further comprising means for generating a control signal to control the means for selectively creating.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. (canceled)
2. A method comprising:
retrieving, by a secure device, personalized unit data and a sequence number stored in a memory of the secure device;
generating, by the secure device, a first decryption key based on the personalized unit data and the sequence number, wherein generating the first decryption key comprises executing at least a portion of a key generation algorithm a number of times based on the sequence number; and
decrypting, by the secure device, first content using the first decryption key.
3. The method of claim 2, further comprising:
after decrypting the first content using the first decryption key, changing the sequence number stored in the memory of the secure device to an updated sequence number;
receiving second content;
in response to receiving the second content, generating a second decryption key based on the personalized unit data and the updated sequence number, the generating comprising executing at least a portion of the key generation algorithm a number of times based on the updated sequence number, wherein the second decryption key is different than the first decryption key; and
decrypting the second content using the second decryption key.
4. The method of claim 3, wherein generating the first decryption key comprises generating a predetermined number (N) of decryption keys using the key generation algorithm and using the Nth generated decryption key as the first decryption key, and
wherein generating the second decryption key comprises generating N\u22121 decryption keys using the key generation algorithm and using the Nth\u22121 generated decryption key as the second decryption key.
5. The method of claim 2, further comprising:
determining that the decryption of the first content using the first decryption key was not successful;
determining that the sequence number in the memory of the secure device should not be changed, based on the determination that the decryption of the first content using the first decryption key was not successful;
receiving second content; and
decrypting the second content using the first decryption key.
6. The method of claim 2, wherein the personalized unit data is based on a serial number of the secure device.
7. The method of claim 2, further comprising:
determining, by the secure device, that the decryption of the first content using the first decryption key was successful; and
in response to determining that the decryption of the first content using the first decryption key was successful, incrementing or decrementing the sequence number stored within the memory of the secure device.
8. The method of claim 2, wherein the first content corresponds to a first software code image, and wherein the method further comprises:
executing the first software code image at the secure device;
determining, by the secure device, that the execution of the first code image was successful; and
in response to determining that the execution of the first code image was successful, incrementing or decrementing the sequence number stored within the memory of the secure device.
9. The method of claim 2, further comprising:
incrementing or decrementing the sequence number stored within the memory of the secure device, wherein the sequence number is incremented or decremented regardless of whether the decryption of the first content using the first decryption key was successful.
10. The method of claim 2, wherein the personalized unit data is based on at least a type or version of software currently loaded on the secure device.
11. A method comprising:
retrieving from a secure memory, by a computing device, first personalized unit data and a first sequence number associated with a first secure processor;
generating, by the computing device, a first encryption key based on the first personalized unit data and the first sequence number, wherein generating the first encryption key comprises executing at least a portion of a key generation algorithm a number of times based on the first sequence number; and
encrypting, by the computing device, a first content download using the first encryption key; and
transmitting, by the computing device, the encrypted first content download to the first secure processor.
12. The method of claim 11, further comprising:
retrieving second personalized unit data associated with a second secure processor;
generating a second encryption key based on the second personalized unit data associated with the second secure processor, wherein the second encryption key is different from the first encryption key;
encrypting the first content download using the second encryption key; and
transmitting the first content download encrypted with the second encryption key to the second secure processor.
13. The method claim 11, further comprising:
after transmitting the encrypted first content download to the first secure processor, changing the first sequence number to an updated first sequence number; and
storing at the computing device the updated first sequence number in a memory, the updated first sequence number corresponding to the number of previous content downloads performed at the first secure processor.
14. The method of claim 13, further comprising:
generating a second encryption key based on the personalized unit data associated with the first secure processor and the updated first sequence number, the generating comprising iteratively executing at least a portion of the key generation algorithm a number of times based on the updated first sequence number, wherein the second encryption key is different than the first encryption key;
encrypting a second content download using the second encryption key; and
transmitting the encrypted second content download to the first secure processor.
15. The method of claim 11, further comprising:
storing, at the computing device, a plurality of unique personalized unit data and a plurality of content download sequence numbers, wherein each unique personalized unit data and each content download sequence number correspond to one of a plurality of secure processors associated with the computing device.
16. The method of claim 11, further comprising:
receiving, by the computing device, a confirmation message from the first secure processor, the confirmation message indicating that the encrypted first content was successfully decrypted by the first secure processor; and
in response to receiving the confirmation message indicating that the encrypted first content was successfully decrypted by the first secure processor, incrementing or decrementing the first sequence number associated with the first secure processor in a memory of the computing device.
17. The method of claim 11, further comprising:
receiving, by the computing device, a confirmation message from the first secure processor, the confirmation message indicating that the encrypted first content was successfully executed by the first secure processor; and
in response to receiving the confirmation message indicating that the encrypted first content was successfully executed by the first secure processor, incrementing or decrementing, in a memory of the computing device, the first sequence number associated with the first secure processor.
18. The method of claim 11, further comprising:
incrementing or decrementing, in a memory of the computing device, the first sequence number associated with the first secure processor, wherein the first sequence number is incremented or decremented regardless of whether the encrypted first content was successfully decrypted or successfully executed by the first secure processor.
19. A method, comprising:
encrypting, by a control server, a first content download for a first secure processor, wherein the encrypting is based on a first sequence number associated with the first secure processor;
transmitting, by the control server, the encrypted first content download to the first secure processor;
receiving, by the control server, a confirmation message indicating that the encrypted first content download was successfully executed by the first secure processor; and
in response to receiving the confirmation message, updating the first sequence number corresponding to the first secure processor within a secure memory of the control server.
20. The method of claim 19, wherein encrypting the first content download comprises:
generating a first encryption key based on the first sequence number and based on first personalized unit data associated with the first secure processor, said generating comprising executing at least a portion of a key generation algorithm a number of times based on the first sequence number; and
encrypting the first content download using the first encryption key.
21. The method of claim 19, wherein updating the first sequence number comprises incrementing or decrementing the first sequence number within the secure memory of the control server, in response to receiving the confirmation message.