1. A coating device for coating a coating liquid on a surface of a belt body which is conveyed in a certain direction, the coating device comprising:
a first side bar which extends along a transverse direction of a conveyance plane, which conveyance plane includes a conveyance path of the belt body;
a second side bar at a downstream side relative to the first side bar, which extends in parallel with the first side bar;
a first side coating liquid supply channel, which supplies the coating liquid at an upstream side at the first side bar;
an inter-bar liquid-pooling section located between the first side bar and the second side bar, which accumulates the coating liquid at a time of coating of the coating liquid; and
a connecting channel which channels the coating liquid from the inter-bar liquid-pooling section to the first side coating liquid supply channel so as to lower the coating liquid in the inter-bar liquid-pooling section,
wherein an air-liquid boundary surface is formed between the coating liquid and air, between the belt body and the inter-bar liquid-pooling section.
2. The coating device of claim 1, further comprising a second side coating liquid supply channel which supplies the coating liquid at a downstream side at the second side bar, wherein a supplied amount of the coating liquid at the second side coating liquid supply channel is controlled independently from a supplied amount of the coating liquid at the first side coating liquid supply channel.
3. The coating device of claim 1, wherein the first side bar and the second side bar are rotatable in a direction equal to a conveyance direction of the belt body.
4. The coating device of claim 3, wherein a separation of central axes of the first side bar and the second side bar is set in accordance with composition and viscosity of the coating liquid.
5. The coating device of claim 4, wherein the separation of the central axes of the first side bar and the second side bar is set such that a duration from a time at which the belt body passes the first side bar until a time at which the belt body passes the second side bar is not more than 0.02 seconds.
6. The coating device of claim 3, further comprising a pedestal for supporting the first side bar and the second side bar.
7. The coating device of claim 6, further comprising a first side dam plate at an upstream side of the pedestal and a second side dam plate at a downstream side of the pedestal, wherein the first side dam plate and the second side dam plate are disposed to be parallel with the pedestal.
8. The coating device of claim 7, wherein the first side coating liquid supply channel is formed between the first side dam plate and the pedestal.
9. The coating device of claim 1, further comprising a first side dam-form member provided standing at an upstream side relative to the first side bar, the first side dam-form member forming a portion of a wall face of wherein a peak portion of the first side dam-form member includes a height which is equal to or higher than a height of a bottom face of the inter-bar liquid-pooling section and which is lower than the conveyance plane.
10. The coating device of claim 1, wherein the connecting channel comprises a coating liquid suction opening portion which opens along the transverse direction of the inter-bar liquid-pooling section, across substantially the whole width of the inter-bar liquid-pooling section.
11. The coating device of claim 10, wherein the coating liquid suction opening portion comprises a continuous slit-form opening portion.
12. The coating device of claim 1, wherein the connecting channel comprises: a vertical channel which opens at the inter-bar liquid-pooling section along a direction which is orthogonal with respect to the conveyance direction of the belt body; and a horizontal channel which is provided in a horizontal direction from a lower end of the vertical channel toward the first side coating liquid supply channel.
13. The coating device of claim 12 wherein the vertical channel opens in the form of a slit.
14. The coating device of claim 12 wherein the horizontal channel comprises a slit form which is divided into at least two divisions in the transverse direction.
15. The coating device of claim 12 wherein the horizontal channel comprises numerous mutually parallel holes.
16. The coating device of claim 12 wherein the vertical channel comprises openings in the form of at least one row of holes.
17. A coating method for coating a coating liquid at a surface of a belt body; the method comprising:
conveying the belt body in a certain direction;
forming an inter-bar liquid-pooling section between a first side bar, which extends along a transverse direction of a conveyance plane, and a second side bar, which extends in parallel with the first side bar at a downstream side of the first side bar;
supplying the coating liquid to an upstream side of the first side bar;
supplying the coating liquid to a downstream side of the second side bar; and using the first side bar and the second side bar to coat the coating liquid at the surface.
18. The coating method of claim 17 further comprising the step of, during the coating of the coating liquid, forming an air-liquid boundary surface, which is a boundary surface between the coating liquid and air, at the inter-bar liquid-pooling section.
19. The coating method of claim 17 further comprising controlling the supplying of the coating liquid to an upstream side of the first side bar independently from the supplying of the coating liquid to a downstream side of the second side bar.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. (canceled)
2. A memory device comprising:
a plurality of global bit lines extending along a first direction;
a pair of word lines separated from each other, extending along a second direction;
a first bit line between the pair of word lines, extending along a third direction different from the first direction and the second direction;
first variable resistivity layers between the first bit line and each word line of the pair of word lines; and
a first selector between the first bit line and one of the plurality of global bit lines,
wherein the first selector includes:
a first semiconductor layer coupled with the first bit line and the one of the plurality of global bit lines, and
a pair of gates on two side surfaces of the first semiconductor layer facing each other in the first direction with first gate insulating layers therebetween.
3. The device according to claim 2,
wherein the pair of word lines includes a first word line and a second word line, and the pair of gates includes a first gate and a second gate, and
the device further comprises:
a third word line separated from the pair of word lines and extending along the second direction, the second word line being between the first word line and the third word line;
a second bit line between the second word line and the third word line, and extending along the third direction;
second variable resistivity layers between the second word line and the second bit line, and between the second bit line and the third word line; and
a second selector between the second bit line and one of the global bit lines, wherein the second selector includes:
a second semiconductor layer coupled with the second bit line and the one of the plurality of global bit lines, and
a third gate on one side surface of the second semiconductor layer with a second gate insulating layer therebetween, and
wherein the second gate contacts another side surface of the second semiconductor layer with the second gate insulating layer interposed therebetween, and the one side surface of the second semiconductor layer and the another side surface of the second semiconductor layer face each other in the first direction.
4. The device according to claim 2, wherein a plurality of word line layers are stacked along the third direction, and each of the word line layers of the plurality of word line layers includes the pair of word lines,
the first semiconductor layer includes a source region, a channel region, and a drain region, and
the source region, the channel region, and the drain region are arranged along the third direction.
5. The device according to claim 2, wherein the first direction is substantially perpendicular to the second direction,
the second direction is substantially perpendicular to the third direction, and
the third direction is substantially perpendicular to the first direction.
6. The device according to claim 2, wherein one of the pair of the gates is vertically aligned to the first bit line, and another of the pair of the gates is vertically aligned to another bit line,
the first semiconductor layer includes a source region contacting the one of the global bit lines and a channel region on the source region, and
a part of one end surface of the first selector contacts one end surface of the first bit line, and a remaining part of the one end surface of the first selector contacts an insulating film between the first bit line and the other bit line and is vertically aligned with one of the pair of the word lines.
7. The device according to claim 2, wherein a surface of one end of the first selector partially contacts the first bit line and provides a current path therebetween.
8. The device according to claim 2, further comprising:
a memory cell array, which includes a plurality of memory cell pillars arranged along a direction perpendicular to the first direction; and
a hook-up region,
wherein each of the plurality of memory cell pillars includes the pair of word lines, the first bit line, and the first variable resistivity layers,
the pair of the gates is shared by the plurality of the memory cell pillars,
the pair of the gates extends to the hook-up region,
the pair of the gates includes a first gate and a second gate, and
the first gate and the second gate are coupled to each other in the hook-up region.
9. A memory device comprising:
a plurality of global bit lines extending along a first direction;
a pair of word lines extending along a second direction, and separated from each other;
a first bit line between the pair of word lines, extending along a third direction different from the first direction and the second direction;
a pair of gates separated from each other in parallel in the first direction, and separated from the pair of word lines in the third direction;
first variable resistivity layers between the first bit line and each word line of the pair of word lines; and
a pair of gate insulating layers between the first bit line and the pair of gates,
wherein the first bit line includes a first semiconductor layer coupled with the gate insulating layers in a part thereof, the first semiconductor layer also being coupled with one of the plurality of global bit lines.
10. The device according to claim 9,
wherein the pair of word lines includes a first word line and a second word line, the pair of gates includes a first gate and a second gate, and the pair of gate insulating layers includes a first gate insulating layer and a second gate insulating layer, and
the device further comprises:
a third word line separated from the pair of word lines and extending along the second direction, the second word line being between the first word line and the third word line;
a second bit line between the second word line and the third word line; and
extending along the third direction;
a third gate;
second variable resistivity layers between the second word line and the second bit line and between the second bit line and the third word line; and
a third gate insulating layer,
wherein the first gate insulating layer is between the first gate and the first bit line, the second gate insulating layer is between the second gate and the first bit line, and the third gate insulating layer is between the third gate and the second bit line, and
wherein the second bit line includes a second semiconductor layer coupled with the third gate insulating layer in a part thereof, the second semiconductor layer also being coupled with one of the plurality of global bit lines, and the third gate faces the second gate with the second semiconductor layer interposed therebetween.
11. The device according to claim 9, wherein a plurality of word line layers are stacked along the third direction, and each of the word line layers of the plurality of word line layers includes the pair of word lines,
the first bit line further includes a source region and a drain region, and
the source region, the first semiconductor layer, and the drain region are arranged along the third direction.
12. The device according to claim 9, wherein the first direction is substantially perpendicular to the second direction,
the second direction is substantially perpendicular to the third direction, and
the third direction is substantially perpendicular to the first direction.
13. The device according to claim 9, wherein the first bit line further includes a source region coupled with the one of the plurality of global bit lines, and a drain region on the first semiconductor layer,
the first semiconductor layer is on the source region, and
the drain region overlaps, in the first direction, with the first semiconductor layer in a partial region thereof.
14. The device according to claim 9, wherein a surface of one end of the first selector partially contacts the first bit line and provides a current path therebetween.
15. The device according to claim 9, further comprising:
a memory cell array, which includes a plurality of memory cell pillars arranged along a direction perpendicular to the first direction; and
a hook-up region,
wherein each of the plurality of memory cell pillars includes the pair of word lines, the first bit line, and the first variable resistivity layers,
the pair of gates is shared by the plurality of the memory cell pillars, and extends to the hook-up region,
the pair of gates includes a first gate and a second gate, and
the first gate and the second gate are coupled to each other in the hook-up region.
16. A memory device comprising:
a plurality of global bit lines, each global bit line of the plurality being provided along a first direction;
a plurality of word lines, each word line of the plurality being provided along a second direction;
a plurality of bit lines, each bit line of the plurality being provided along a third direction different from the first and second directions;
a plurality of memory cells including variable resistance layers facing each other on two side surfaces of the bit lines and coupled with mutually different word lines of the plurality of word lines; and
a plurality of selectors, which couple the plurality of bit lines with the plurality of global bit lines,
wherein one of the plurality of selectors includes a semiconductor layer between associated one of the plurality of bit lines and associated one of the plurality of global bit lines, and
a plurality of gates on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
17. The device according to claim 16, wherein a first selector of the plurality of selectors shares a gate of the plurality of gates with a second selector of the plurality of selectors adjacent to the first selector.
18. The device according to claim 17, wherein a plurality of word line layers are stacked along the third direction,
the first selector further includes a source region and a drain region, and
the source region, the semiconductor layer, and the drain region are arranged along the third direction.
19. The device according to claim 16, wherein the first direction is substantially perpendicular to the second direction,
the second direction is substantially perpendicular to the third direction, and
the third direction is substantially perpendicular to the first direction.
20. The device according to claim 17, wherein the first selector further includes a source region coupled with the associated one of the plurality of global bit lines, and a drain region on the semiconductor layer, and coupled with the associated one of the plurality of bit lines,
the semiconductor layer is on the source region, and
the drain region overlaps, in the first direction, with the semiconductor layer in a partial region thereof.
21. The device according to claim 17, wherein a surface of one end of the first selector partially contacts the associated one of the plurality of bit lines and provides a current path therebetween.
22. The device according to claim 16, further comprising:
a memory cell array, which includes the plurality of memory cells; and
a hook-up region,
wherein each of the plurality of gates is arranged along a direction perpendicular to the first direction and is shared by the plurality of the selectors,
the plurality of gates extends to the hook-up region, and
a first one of the gates and a second one of the gates face each other with the semiconductor layer interposed therebetween, and are coupled to each other in the hook-up region.