1. A circuitry for establishing and automatically maintaining a predetermined duty cycle of a control signal, comprising:
(a) a phase detector having a first input coupled to receive a data clock signal and a second input coupled to a synchronization conductor to receive a data synchronization signal, the phase detector producing a delay control signal having a value indicative of a phase difference between the data clock signal and the data synchronization signal;
(b) a first delay circuit for producing a first delayed signal which is delayed relative to the data clock signal by an amount corresponding to a value of the delay control signal, the delay is determined by utilizing a feedback loop for sensing the duty cycle of the control signal; and
(c) a second delay circuit having an input receiving the first delayed signal and also having an output for producing the control signal by delaying the first delayed signal an amount which causes the control signal to have a predetermined duty cycle.
2. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 1 wherein the control signal is a clock signal.
3. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 1 wherein the control signal is a digital signal.
4. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 1 wherein a delay locked loop adjusts the delay of the first delayed signal to achieve a condition wherein amounts of time that the logic levels of the data synchronization signal and the data clock signal are equal is precisely equal to amounts of time that the logic levels of the data synchronization signal and the data clock signal are opposite.
5. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 1 wherein the first delay circuit delays the first delayed signal by an amount corresponding to an average value of the delay control signal.
6. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 1 wherein the phase detector operates to determine when the data clock signal and the data synchronization signal are at different logic levels.
7. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 6 wherein the phase detector includes an exclusive ORing circuit which produces the delay control signal as a first logic level if the data clock signal and the data synchronization signal are at different logic levels and produces the delay control signal as a second logic level if the data clock signal and the data synchronization signal are at the same logic level.
8. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 1 including a first storage element having a data input, a control input, a data output coupled to a first data bus, and a synchronization conductor conducting the data synchronization signal in synchronization with data on the first data bus.
9. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 8 including a second storage element having a data input coupled to the first data bus, a clock input coupled to the data clock signal, and a data output coupled to a second data bus.
10. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 8 wherein the first data bus is a parallel data bus and wherein a sufficient portion of the synchronization conductor is physically grouped with other conductors of the first data bus to ensure that the data synchronization signal is precisely synchronized with the data appearing at the input of a second storage element.
11. The circuitry for establishing and automatically previously a predetermined duty cycle of the control signal as recited in claim 8 wherein the second delay circuit introduces a delay which causes a delay locked loop including the phase detector, the first delay circuit, the second delay circuit, and the first storage element to cause the control signal to have a 50% duty cycle.
12. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 11 wherein the second delay circuit includes a third delay circuit having a first input coupled to receive the first delayed signal, a second input, and an output coupled to the output of the second delay circuit, a filter coupled to filter the control signal and produce an output signal which represents an average value of the control signal, and an operational amplifier having a first input coupled to receive the average value of the control signal, a reference voltage circuit producing a reference voltage on a second input of the operational amplifier, an output of the operational amplifier producing a duty cycle control signal on the second input of the third delay circuit.
13. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 12 wherein the filter is a 3 pole low pass filter.
14. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 8 wherein the control signal is a double data rate signal which clocks successive bits of data into the first storage element in response to rising edges and in response to falling edges, respectively, of the control signal.
15. The circuitry for establishing and automatically maintaining a predetermined duty cycle of the control signal as recited in claim 14 wherein the data clock signal and the data synchronization signal are double data rate signals.
16. A method of establishing and automatically maintaining a predetermined duty cycle of a control signal, the method comprising:
(a) providing a data clock signal on a first input of a phase detector circuit and applying a data synchronization signal to a second input of the phase detector circuit and operating the phase detector circuit to produce a delay control signal having a value indicative of a phase difference between the data clock signal and the data synchronization signal;
(b) producing a delayed clock signal by delaying the data clock signal in response to the delay control signal; and
(c) producing the control signal by delaying the first delayed signal an amount which causes the control signal to have a predetermined duty, the delay is determined by utilizing a feedback loop for sensing the duty cycle of the control signal.
17. The method of claim 16 wherein step (c) includes producing the first delayed signal so it is delayed relative to the data clock signal by an amount corresponding to an average value of the delay control signal.
18. The method of claim 17 wherein step (b) includes integrating the delay control signal to produce the average value.
19. A circuitry for establishing and automatically maintaining a predetermined duty cycle of a control signal, comprising:
(a) means for providing a data clock signal on a first input of a phase detector circuit and applying a data synchronization signal to a second input of the phase detector circuit and operating the phase detector circuit to produce a delay control signal having a value indicative of a phase difference between the data clock signal and the data synchronization signal;
(b) means for producing a delayed clock signal by delaying the data clock signal in response to the delay control signal; and
(c) means for producing the control signal by delaying the first delayed signal an amount which causes the control signal to have the predetermined duty cycle, the delay is determined by utilizing a feedback loop for sensing the duty cycle of the control signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A communication condition change detection method comprising:
obtaining a graph representing a communication condition at a first timing and at a second timing, the graph including a plurality of nodes representing information entities that transmit, forward, and receive information and a plurality of edges representing communication between the plurality of nodes;
detecting an edge that is added between the first timing and the second timing among the edges;
calculating, by a processor, probabilities that information is transmitted from each node to nodes coupled to the added edge;
selecting a subset of the plurality of nodes based on the calculated probabilities;
selecting nodes included in the subset as starting points of information;
calculating first probabilities that information is transmitted from the selected nodes to each node based on the graph obtained at the first timing and second probabilities that information is transmitted from the selected nodes to each node based on the graph obtained at the second timing; and
detecting a change in the communication condition between the first timing and the second timing by comparing the first probabilities with the second probabilities.
2. The communication condition change detection method according to claim 1, wherein:
the obtaining includes detecting two or more added edges; and
the calculating includes calculating probabilities that information is transmitted from each node to a plurality of nodes each coupled to any of the two or more added edges, and selecting the subset based on a highest probability among the probabilities calculated for each node serving as a starting point.
3. The communication condition change detection method according to claim 1, wherein:
the obtaining includes detecting two or more added edges; and
the calculating includes extracting an edge included in a subgraph that satisfies a predetermined condition from the two more added edges, and selecting nodes coupled to the extracted edge as end points of information, and calculating the probabilities that information is transmitted from each node.
4. The communication condition change detection method according to claim 3, wherein the calculating includes calculating, for each node serving as a starting point, a sum of the probabilities that information is transmitted to a plurality of nodes coupled to the extracted edge, and selecting the subset based on the sum.
5. The communication condition change detection method according to claim 3, wherein the subgraph that satisfies the predetermined condition is a clique having an edge between any two nodes to connect the two nodes.
6. An information processing apparatus for detecting a change of communication condition, the information processing apparatus comprising:
a memory configured to store a graph representing a communication condition at a first timing and at a second timing, the graph including a plurality of nodes representing information entities that transmit, forward, and receive information and a plurality of edges representing communication between the plurality of nodes; and
a processor configured to perform a process including:
detecting an edge that is added between the first timing and the second timing among the edges,
calculating probabilities that information is transmitted from each node to nodes coupled to the added edge,
selecting a subset of the plurality of nodes based on the calculated probabilities,
selecting nodes included in the subset as starting points of information,
calculating first probabilities that information is transmitted from the selected nodes to each node based on the graph obtained at the first timing and second probabilities that information is transmitted from the selected nodes to each node based on the graph obtained at the second timing, and
detecting a change in the communication condition between the first timing and the second timing by comparing the first probabilities with the second probabilities.
7. A non-transitory computer-readable storage medium storing a computer program that causes a computer to perform a process comprising:
obtaining a graph representing a communication condition at a first timing and at a second timing, the graph including a plurality of nodes representing information entities that transmit, forward, and receive information and a plurality of edges representing communication between the plurality of nodes;
detecting an edge that is added between the first timing and the second timing among the edges;
calculating probabilities that information is transmitted from each node to nodes coupled to the added edge;
selecting a subset of the plurality of nodes based on the calculated probabilities;
selecting nodes included in the subset as starting points of information;
calculating first probabilities that information is transmitted from the selected nodes to each node based on the graph obtained at the first timing and second probabilities that information is transmitted from the selected nodes to each node based on the graph obtained at the second timing; and
detecting a change in the communication condition between the first timing and the second timing by comparing the first probabilities with the second probabilities.