1. A semiconductor chip comprising:
an electrode pad portion formed on a face of a substrate;
a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;
a barrier metal layer formed on the electrode pad portion;
a bump electrode on the barrier metal layer; and
a second protection layer covering a region on the first protection layer and a region on the electrode pad portion,
wherein the first protection layer has a step part formed therein as a result of the first protection layer overlapping the part of the electrode pad portion,
wherein the barrier metal layer has a circumferential end part thereof formed outward of the first opening as seen in a plan view,
wherein the bump electrode is bonded to the barrier metal layer,
wherein the barrier metal layer is on the electrode pad portion with a peripheral part of the barrier metal layer located over the second protection layer,
wherein the second protection layer has a second opening through which the top face of the electrode pad portion is exposed and that has an opening width smaller than the first opening, and
wherein a rim part of the second protection layer defining the second opening has an inclined shape, an upper surface of the second protection layer has an arc surface along a lower surface of the barrier metal layer, and a center point of a curvature of the arc surface as seen in a sectional view is located on a first protection layer side of the arc surface.
2. The semiconductor chip according to claim 1, wherein the barrier metal layer has a circumferential end part thereof formed outward of the step part as seen in a plan view and extend upwardly along the second protection layer.
3. The semiconductor chip according to claim 1, wherein a center of the barrier metal layer is lower than the rim portion of the barrier metal layer.
4. The semiconductor chip according to claim 1, wherein the second protective layer intrude into a space between the barrier metal layer and the first protective layer so that the second protective layer is interdigitate with the first protection layer.
5. The semiconductor chip according to claim 1, the bump electrode is bonded to the barrier metal layer.
6. The semiconductor chip according to claim 1, wherein the bump electrode has a portion which, as seen in a plan view, protrudes out from a side surface of the barrier metal layer.
7. The semiconductor chip according to claim 1, wherein the first opening has an opening width of about 85 \u03bcm to about 95 mm, and wherein the second opening has an opening width of about 55 \u03bcm to about 65 mm.
8. The semiconductor chip according to claim 1, wherein the second protection layer is made of polyimide.
9. A semiconductor device comprising:
the semiconductor chip according to claim 1; and
a printed circuit board on which the semiconductor chip is mounted to form an electric device.
10. A semiconductor chip comprising:
an electrode pad on a surface of a substrate;
a first protection layer disposed partially on the surface of the substrate and overlapping part of the electrode pad, the first protection layer having a first opening;
a second protection layer covering a region on the first protection layer and a region on the electrode pad, the second protection layer having a second opening that has a width smaller than a width of the first opening;
a barrier metal layer on the electrode pad, wherein an interface between the barrier metal layer and the electrode pad is located within the first opening and within the second opening,
a bump electrode bonded to the barrier metal layer, and
wherein a peripheral part of the barrier metal layer is on the second protection layer; and
wherein an upper surface of the second protection layer has an arc surface in contact with a surface of the barrier metal layer, and a center point of a curvature of the arc surface as seen in a sectional view is located on a substrate side of the arc surface, and
wherein the upper surface and a lower surface of the barrier metal layer has a curved shape extending along the second protective layer so that a center point of a curvature of the curved shape as seen in a sectional view is located on a substrate side of the curved shape.
11. The semiconductor chip according to claim 10, wherein the barrier metal layer has a circumferential end part thereof formed outward of the step part as seen in a plan view and extend upwardly along the second protection layer.
12. The semiconductor chip according to claim 10, wherein a center of the barrier metal layer is lower than a rim portion of the barrier metal layer.
13. The semiconductor chip according to claim 10, wherein the second protective layer intrude into a space between the barrier metal layer and the first protective layer so that the second protective layer is interdigitate with the first protection layer.
14. The semiconductor chip according to claim 10, the bump electrode is disposed on the barrier metal layer.
15. The semiconductor chip according to claim 10, wherein the bump electrode has a portion which, as seen in a plan view, protrudes out from a side surface of the barrier metal layer.
16. The semiconductor chip according to claim 10, wherein the first opening has an opening width of about 85 \u03bcm to about 95 mm, and wherein the second opening has an opening width of about 55 \u03bcm to about 65 mm.
17. The semiconductor chip according to claim 10, wherein the second protection layer is made of polyimide.
18. A semiconductor device comprising:
the semiconductor chip according to claim 10; and
a printed circuit board on which the semiconductor chip is mounted to form an electric device.
19. A semiconductor chip comprising:
an electrode pad on a surface of a substrate;
a first protection layer disposed partially on the surface of the substrate and overlapping part of the electrode pad, the first protection layer having a first opening;
a second protection layer covering a region on the first protection layer and a region on the electrode pad, the second protection layer having a second opening that has a width smaller than a width of the first opening;
a barrier metal layer on the electrode pad, wherein an interface between the barrier metal layer and the electrode pad is located within the first opening and within the second opening,
a bump electrode bonded to the barrier metal layer, and
wherein a peripheral part of the barrier metal layer is on the second protection layer; and
wherein an upper surface of the second protection layer has an arc surface in contact with a surface of the barrier metal layer, and a center point of a curvature of the arc surface as seen in a sectional view is located on a substrate side of the arc surface,
wherein the upper surface and a lower surface of the barrier metal layer has a curved shape extending along the second protective layer so that a center point of a curvature of the curved shape as seen in a sectional view is located on a substrate side of the curved shape,
wherein the barrier metal layer has a circumferential end part thereof formed outward of the step part as seen in a plan view and extend upwardly along the second protection layer, and
wherein a center of the barrier metal layer is lower than the rim portion of the barrier metal layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A self-processing integrated damage assessment sensor system comprising:
a sensor for producing signals responsive to structural anomalies;
a database module for storing data representative of the signals produced by said sensor;
an analysis module responsive to signals from said sensor and data stored in said database module for producing results describing the structural anomalies sensed by said sensor; and
a communications module for transmitting signals based at least in part on the signals produced by said analysis module,
wherein said sensor, said database module, said analysis module and said communications module are commonly housed.
2. The self-processing integrated damage assessment sensor system of claims 1, wherein said sensor comprises a passive device.
3. The self-processing integrated damage assessment sensor system of claim 2, wherein said sensor is selected from the group consisting of resistors, capacitors, and resistor-capacitor series combinations.
4. The self-processing integrated damage assessment sensor system of claim 1, wherein the sensor comprises an active device.
5. The self-processing integrated damage assessment sensor system of claim 4, wherein the sensor comprises a piezoelectric device.
6. The self-processing integrated damage assessment sensor system of claim 5, wherein the sensor comprises a piezoelectric wafer active sensor.
7. The self-processing integrated damage assessment sensor system of claim 1, further comprising:
an electromechanical impedance module configured to receive signals from said sensor, to measure a local impedance spectrum over a preselected range of frequencies, and to provide measurement data for use by said analysis module.
8. The self-processing integrated damage assessment sensor system of claim 7, wherein said database module comprises a spectral database module comprising a memory configured to receive measurement data from said electromechanical impedance module.
9. The self-processing integrated damage assessment sensor system of claim 1, wherein said communication module comprises a wireless interface module configured to transmit signals identifying selected of the signal source and signal location.
10. A method of assessing structural health using a self-contained integrated sensor system, comprising the steps of:
providing a sensor for producing signals;
measuring impedance spectra over a selected frequency ranged based on the signals;
storing data based on said step of measuring;
analyzing the measured impedance spectra to determine the presence of preselected selected signal characteristics indicative of structural health;
providing selected of said data as a portion of the measured impedance spectra in the step of analyzing; and producing signals indicative of anomalies in structural health.
11. The method of claim 10, further comprising the step of transmitting signals based at least in part on the results of the step of analyzing.
12. The method of claim 10, further comprising the step of wirelessly transmitting signals based at least in part on the results of the step of analyzing.
13. The method of claim 10, wherein the step of providing a sensor comprises providing a passive sensor.
14. The method of claim 10, wherein the step of providing a sensor comprises providing an active sensor.
15. The method of claim 14, wherein the step of providing an active sensor comprises providing a piezoelectric wafer active sensor.