1. A method comprising:
mapping a shared memory into first and second virtual address spaces, with the shared memory holding buffer data structures and non-buffer data structures, with the buffer data structures and non-buffer data structures shared between InputOutput (IO) devices which send and receive packets and a Central Processing Unit (CPU);
setting a cache attribute for the first virtual address space and utilizing the cache write through algorithm when writing cached data with addresses in the first virtual address space, where the first virtual address space is utilized only by the CPU and the CPU utilizes addresses in the first virtual address space to access only buffer data structures;
reporting addresses in the first virtual address space to code executed by the CPU which implements switching;
returning pointers to buffer data structures, which store packet data, where pointers returned point to addresses in the first virtual address space when allocating memory;
setting a non-cache attribute for the second virtual address space, where non-buffer data structures held in the shared memory are accessed utilizing addresses in the second address space;
converting a returned pointer to a buffer data structure from a pointer to an address in the first virtual address space to a converted pointer to a corresponding address in the second virtual address space prior to passing the pointer from the CPU to an IO device;
at the IO device, using the converted pointer to access packet data stored in a buffer data structure in the shared memory; and
at the CPU, invalidating the cache lines corresponding to the addresses of a received packet before accessing data in the received packet.
2. The method of claim 1 further comprising the step of:
using physical addresses of the shared IO memory in the second virtual address space.
3. The method of claim 1 further comprising the step of:
mapping the first virtual address space so that only a most significant bit is different from the physical address.
4. The method of claim 3 where said step of converting comprises the step of:
changing a bit value of the most significant bit in the address pointed to by the return pointer.
5. The method of claim 1 further comprising the steps of:
converting pointers returned to addresses of non-buffer data structures in the first virtual address space in shared IO memory to converted pointers to corresponding addresses in the second virtual address space; and
utilizing the converted pointers at the CPU to access said non-buffer data structures.
6. One or more computer readable storage media encoded with software comprising computer executable instructions and when the software is executed operable to:
map a shared to memory into first and second virtual address spaces, with the shared memory including buffer data structures and non-buffer data structures, with the buffer data structures and non-buffer data structures shared between InputOutput (IO) devices which send and receive packets and a Central Processing Unit (CPU);
set a cache attribute for the first virtual address space and utilize the cache write through algorithm when writing cached data with addresses in the first virtual address space, where the first virtual address space and utilize the cache write through algorithm when writing cached data with addresses int he first virtual address space, where the first virtual address space is utilized only by the CPU and the CPU utilizes addresses int he first virtual address space to access only buffer data structures;
report addresses in the first virtual address space to code executed by the CPU which implements switching;
return pointers to buffer data structures, which store packet data, where pointers returned point to addresses in the first virtual address space when allocating memory;
set a non-cache attribute for the second virtual address space, where non-buffer data structures held in the shared memory are accessed utilizing addresses in the second virtual address space;
convert a returned pointer to a buffer data structure from a pointer to an address in the first virtual address space to a converted pointer to a corresponding address in the second virtual address space prior to passing the pointer from the CPU to an IO device;
cause said IO device to use the converted pointer to access packet data stored in a buffer data structure in the shared memory; and
cause the CPU to invalidate cache lines corresponding to the addresses of a received packet before accessing data in the received packet.
7. The computer readable storage media of claim 6 encoded with software when executed further operable to:
use physical addresses of the shared IO memory in the second virtual address space.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A hearing aid, comprising:
an input system;
an output system;
a solid state tunneling magnetic sensor generating a magnetic field signal;
a processor configured to be programmed to process signals from the input system and provide the processed signals to the output system,
wherein the processor is configured to receive the magnetic field signal from the sensor, and is programmable to select parameters for signal processing using a first digital filter or a second digital filter, the selection of either the first digital filter or the second digital filter based at least in part on the magnetic field signal.
2. The hearing aid of claim 1, wherein the solid state tunneling magnetic sensor includes a spin dependent tunneling (SDT) device.
3. The hearing aid of claim 2, wherein the SDT device is fabricated using photolithography.
4. The hearing aid of claim 2, wherein the SDT device includes a saturation field range from 0.1 to 10 kAm.
5. The hearing aid of claim 2, wherein the SDT device is configured to be used as a hearing aid switch.
6. The hearing aid of claim 2, wherein the SDT device is configured to provide hearing aid programming signals.
7. The hearing aid of claim 2, wherein the SDT device includes a giant magnetoresistivity (GMR) material layer, and wherein the SDT device includes a conduction path perpendicular to a plane of the GMR material layer.
8. The hearing aid of claim 1, wherein the input system includes a microphone.
9. The hearing aid of claim 1, wherein the input system is configured to switch from an acoustic input to a magnetic input based on the magnetic field signal.
10. The hearing aid of claim 9, wherein the magnetic input includes a telecoil.
11. A hearing aid, comprising:
a power source;
a hearing aid circuit; and
a solid state tunneling magnetic sensor configured to connect the power source to the hearing aid circuit, wherein the sensor is configured to disconnect the power source from the hearing aid circuit when in the presence of a sufficiently strong magnetic field.
12. The hearing aid of claim 11, wherein the solid state tunneling magnetic sensor includes a spin dependent tunneling (SDT) device.
13. The hearing aid of claim 12, wherein the SDT device is fabricated using photolithography.
14. The hearing aid of claim 12, wherein the SDT device includes a saturation field range from 0.1 to 10 kAm.
15. The hearing aid of claim 11, wherein the power source is a battery.
16. The hearing aid of claim 15, wherein the battery is rechargeable.
17. The hearing aid of claim 12, wherein the SDT device includes a giant magnetoresistivity (GMR) material layer, and wherein the SDT device includes a conduction path perpendicular to a plane of the GMR material layer.
18. The hearing aid of claim 11, further comprising a filter connected to the hearing aid circuit, wherein the solid state tunneling magnetic sensor is configured to electrically disconnect the filter from the hearing aid circuit when in the presence of a sufficiently strong magnetic field.
19. The hearing aid of claim 11, wherein the solid state tunneling magnetic sensor is further configured to operate as a programming circuit to program the hearing aid.
20. The hearing aid of claim 11, further comprising at least one acoustic input connected to the hearing aid circuit, wherein the solid state tunneling magnetic sensor is configured to inhibit the acoustic input in the presence of a magnetic field.