1. A method of disassociating tissue using a dual-compartment bioreactor, which comprises a flexible pouch (1) having two compartments (2, 3) separated by a screen (4), and also at least one inlet opening (5) in communication with one of the compartments (2) and at least one outlet opening (6) in communication with the other compartment (3), comprising the insertion thereof in biological processing equipment, in particular for washing or converting a tissue or cell product, characterized in that it implements, for a tissue dissociation, the use of said bioreactor as a digestion chamber and manual kneading of the flexible pouch for dissociating the tissues during a digestion step in which a digestion solution containing collagenase flows between the inlet (5) and outlet (6) openings of the pouch.
2. The method as claimed in claim 1, characterized in that the tissue dissociation is the sorting of islets of Langerhans and in that the kneading separates the islets of Langerhans.
3. The method as claimed in claim 1, characterized in that the screen (4) has a mesh of between 50 \u03bcm and 600 \u03bcm suitable for the sorting of islets of Langerhans.
4. The method as claimed in claim 1, characterized in that the screen has a pore size that allows only a cell-free liquid to pass through, said liquid being suitable in particular for cell culture or for a method for washing cell suspensions.
5. The method as claimed in claim 1, characterized in that the pouch is used for biological reactions such as cell culture, coculture, or else cell engineering.
6. The method as claimed in claim 1, characterized in that the pouch is used as a washing device in biology, without the need to centrifuge the cell suspension.
7. The method as claimed in claim 1, characterized in that at least one of the compartments has both an inlet opening and an outlet opening.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor memory device comprising:
a semiconductor substrate;
a tunnel insulating film formed on said semiconductor substrate;
an Al2O3 film formed on said tunnel insulating film;
a pair of charge storage layers sandwiching said Al2O3 film therebetween in plain view formed on said tunnel insulating film;
an insulating film formed on said Al2O3 film and said pair of charge storage layers;
a gate electrode formed on said insulating film; and
a source region and a drain region formed as a pair sandwiching said gate electrode in plain view formed on a surface of said semiconductor substrate.
2. The semiconductor memory device according to claim 1, further comprising a sidewall insulating film formed over a side surface of said gate electrode, said insulating film, and said pair of charge storage layers.
3. A semiconductor memory device having a pair of charge storage layers in each memory cell thereof and being capable of storing four values, comprising an Al2O3 film insulating said pair of charge storage layers with each other.
4. The semiconductor memory device according to claim 1, wherein
said charge storage layers are composed of a polycrystalline silicon.
5. The semiconductor memory device according to claim 3, wherein
said charge storage layers are composed of a polycrystalline silicon.
6. The semiconductor memory device according to claim 1, wherein
said tunnel insulating film has a thickness of 3 nm to 9 nm.
7. The semiconductor memory device according to claim 3, wherein
a tunnel insulating film has a thickness of 3 nm to 9 nm.
8. The semiconductor memory device according to claim 1, wherein
said Al2O3 film and said pair of charge storage layers have a thickness of 5 nm to 15 nm.
9. The semiconductor memory device according to claim 3, wherein
said Al2O3 film and said pair of charge storage layers have a thickness of 5 nm to 15 nm.
10. A manufacturing method of a semiconductor memory device comprising the steps of:
forming a tunnel insulating film on a semiconductor substrate;
forming sequentially an Al2O3 film, an insulating film, and a material film of a gate electrode on the tunnel insulating film;
forming a gate electrode by processing the material film of the gate electrode, the insulating film, and the Al2O3 film into a planar shape of the gate electrode;
making a retreat of an outer edge of the Al2O3 film to be smaller than an outer edge of the gate electrode by performing isotropic etching to the Al2O3 film so as to form a pair of spaces under the insulating film;
forming charge storage layers respectively in the pair of spaces; and
forming a source region and a drain region sandwiching the gate electrode in plain view, as a pair, on a surface of the semiconductor substrate.
11. The manufacturing method of the semiconductor memory device according to claim 10, wherein
isotropic etching of the Al2O3 film is performed using a solution of sulfuric acid with hydrogen peroxide during the step of performing isotropic etching to the Al2O3 film.
12. The manufacturing method of the semiconductor memory device according to claim 10, wherein
a polycrystalline silicon film is formed as the charge storage layers.
13. The manufacturing method of the semiconductor memory device according to claim 10, wherein
said step of forming the charge storage layers comprises the steps of:
forming a polycrystalline silicon film all over surface; and
making the polycrystalline silicon film remain in the spaces and forming a sidewall composed of the polycrystalline silicon film over side surfaces of the gate electrode and the insulating film by performing anisotropic etching to the polycrystalline silicon film.
14. The manufacturing method of the semiconductor memory device according to claim 13, wherein
said step of forming the charge storage layers comprises a step of oxidizing the sidewall after the step of performing anisotropic etching to the polycrystalline silicon film.
15. The manufacturing method of the semiconductor memory device according to claim 10, wherein
said step of forming the charge storage layers comprises the steps of:
forming a polycrystalline silicon film all over surface; and
making the polycrystalline silicon film remain only in the spaces by performing anisotropic etching to the polycrystalline silicon film.
16. The manufacturing method of the semiconductor memory device according to claim 15, wherein
said step of forming the charge storage layers comprises the steps of:
forming an insulating film for a sidewall all over surface; and
forming a sidewall insulating film over side surfaces of the gate electrode and the insulating film by etching back the insulating film for the sidewall, after the step of performing anisotropic etching to the polycrystalline silicon film.
17. The manufacturing method of the semiconductor memory device according to claim 10, wherein
the tunnel insulating film has a thickness of 3 nm to 9 nm.
18. The manufacturing method of the semiconductor memory device according to claim 10, wherein
the Al2O3 film and the pair of charge storage layers have a thickness of 5 nm to 15 nm.
19. The manufacturing method of the semiconductor memory device according to claim 11, wherein
the tunnel insulating film has a thickness of 3 nm to 9 nm.
20. The manufacturing method of the semiconductor memory device according to claim 11, wherein
the Al2O3 film and a pair of charge storage layers have a thickness of 5 nm to 15 nm.