1. A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a first silicon oxide film over a surface of a semiconductor substrate by thermally oxidizing said substrate and then forming an oxidation resistant film over said first silicon oxide film, and selectively exposing said surface of said substrate for an element isolation region by removing said oxidation resistant film and said first silicon oxide film;
(b) after said step (a), recessing an end of said first silicon oxide film inward more than an end of said oxidation resistant film;
(c) forming a second silicon oxide film, having a thickness larger than that of said first silicon oxide film, on said surface of said substrate which is exposed after said step (b) by thermally oxidizing said exposed substrate surface including a silicon surface extending from an edge of said first silicon oxide film and under said oxidation resistant film, said second silicon oxide film including a bird’s beak that extends inwardly from the end of said oxidation resistant film;
(d) exposing said surface of said semiconductor substrate in said element isolation region by etching said second silicon oxide film, including said bird’s beak, to form an inclined surface of said substrate at an edge of said element isolation region, wherein said edge of said element isolation region extends inwardly from the end of said oxidation resistant film;
(e) forming a trench in said substrate of said element isolation region by etching said substrate exposed in said step (d) to form a concave surface at said edge of said element isolation region, using said oxidation resistant film as a mask;
(f) after said step (e), cleaning said substrate;
(g) after said step (f), rounding said edge of said element isolation region by thermal oxidation; and
(h) after said step (g), burying said trench with an insulating film by polishing an insulating film formed over said oxidation resistant film and said trench.
2. A method according to claim 1, wherein said concave surface is formed by a recessing of an intermediate portion of said inclined surface in said step (d).
3. A method according to claim 1, wherein a third silicon oxide film is formed on an inner wall of said trench by said thermal oxidation in said step (g).
4. A method according to claim 1, wherein said substrate is over-etched in said removing of said step (a).
5. A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a first silicon oxide film over a surface of a semiconductor substrate by thermally oxidizing said substrate and then forming an oxidation resistant film over said first silicon oxide film, and selectively exposing said surface of said substrate for an element isolation region by removing said oxidation resistant film and said first silicon oxide film;
(b) after said step (a), recessing an end of said first silicon oxide film inward more than an end of said oxidation resistant film;
(c) forming a second silicon oxide film, having a thickness larger than that of said first silicon oxide film, on said surface of said substrate which is exposed after said step (b) by thermally oxidizing said exposed substrate surface including a silicon surface extending from an edge of said first silicon oxide film and under said oxidation resistant film, said second silicon oxide film including a bird’s beak that extends inwardly from the end of said oxidation resistant film;
(d) exposing said surface of said semiconductor substrate in said element isolation region by etching said second silicon oxide film, including said bird’s beak, to form an inclined surface of said substrate at an edge of said element isolation region, wherein said edge of said element isolation region extends inwardly from the end of said oxidation resistant film;
(e) forming a trench in said substrate of said element isolation region by etching said substrate exposed in said step (d) to form a concave surface at said edge of said element isolation region, using said oxidation resistant film as a mask;
(f) after said step (e), rounding said edge of said element isolation region by thermal treatment; and
(g) after said step (f), burying said trench with an insulating film by polishing an insulating film formed over said oxidation resistant film and said trench.
6. A method according to claim 5, wherein said concave surface is formed by a recessing of an intermediate portion of said inclined surface in said step (d).
7. A method according to claim 5, wherein a third silicon oxide film is formed on an inner wall of said trench by said thermal treatment in said step (f).
8. A method according to claim 5, wherein said substrate is over-etched in said removing of said step (a).
9. A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a first silicon oxide film over a surface of a semiconductor substrate by thermally oxidizing said substrate and then forming an oxidation resistant film over said first silicon oxide film, selectively exposing said surface of said substrate for an element isolation region by removing said oxidation resistant film and said first silicon oxide film, and then over-etching the semiconductor substrate that is exposed;
(b) forming a second silicon oxide film, having a thickness larger than that of said first silicon oxide film, on said surface of said substrate which is exposed after said step (a) by thermally oxidizing said exposed substrate surface including a silicon surface extending from an edge of said first silicon oxide film and under said oxidation resistant film, said second silicon oxide film including a bird’s beak that extends inwardly from the end of said oxidation resistant film;
(c) exposing said surface of said semiconductor substrate in said element isolation region by etching said second silicon oxide film, including said bird’s beak, to form an inclined surface of said substrate at an edge of said element isolation region, wherein said edge of said element isolation region extends inwardly from the end of said oxidation resistant film;
(d) forming a trench in said substrate of said element isolation region by etching said substrate exposed in said step (d) to form a concave surface at said edge of said element isolation region, using said oxidation resistant film as a mask;
(e) after said step (d), rounding said edge of said element isolation region by thermal treatment whereby a first sharply inclined surface and a second gently inclined surface are formed at said edge of said element isolation region, such that said second gently inclined surface is formed between said first sharply inclined surface and an inner wall of said trench; and
(f) after said step (e), burying said trench with an insulating film by polishing an insulating film formed over said oxidation resistant film and said trench.
10. A method according to claim 9, further comprising the step of:
between said step (a) and said step (b), recessing an end of said first silicon oxide film inward more than an end of said oxidation resistant film.
11. A method according to claim 9, wherein said concave surface is formed by a recessing of an intermediate portion of said inclined surface in said step (c).
12. A method according to claim 9, wherein a third silicon oxide film is formed on said inner wall of said trench by said thermal oxidation in said step (e).
13. A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a first silicon oxide film over a semiconductor substrate;
(b) forming a first silicon nitride film over said first silicon oxide film;
(c) selectively etching said first silicon nitride film and said first silicon oxide film and over-etching said semiconductor substrate;
(d) recessing an end of said first silicon oxide film inward more than an end of said first silicon nitride film;
(e) forming a second silicon oxide film over the etched semiconductor substrate, after said step (c), wherein said second silicon oxide film extends inward from the end of said first silicon nitride film, and wherein an inwardly extended second silicon oxide film is formed on an etched surface of said semiconductor substrate including a silicon surface, extending from adjacent an edge of said first silicon oxide film and under said first silicon nitride film;
(f) forming an inclined surface in said semiconductor substrate by etching said second silicon oxide film, wherein an edge of said inclined surface extends inwardly from the end of said first silicon nitride film;
(g) etching said semiconductor substrate to form a trench by using said first silicon nitride film as a mask;
(h) rounding a first boundary portion between said inclined surface and a surface of said semiconductor substrate, and a second boundary portion between said inclined surface and a sidewall of said trench; and
(i) burying an insulating film in said trench.
14. A method of manufacturing a semiconductor integrated circuit device according to claim 13, further comprising a step of:
(j) between said steps (g) and (h), washing said substrate.
15. A method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein a method of thermal oxidation is used for said step (h).
16. A method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein at said step (h), a third silicon oxide film is formed over an inner wall of said trench.
17. A method of manufacturing a semiconductor integrated circuit device according to claim 16, further comprising a step of forming a second silicon nitride film over said inner wall of said trench.
18. A method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein said step (i) comprises steps of:
(k) forming an insulating film over said first silicon nitride film and inside said trench; and
(l) polishing said insulating film by a CMP method.
19. A method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein at said step (l), said first silicon nitride film is used as an etching stopper.
20. A method of manufacturing a semiconductor integrated circuit device according to claim 18, further comprising a step of:
(m) after said step (k), annealing said insulating film.
21. A method of manufacturing a semiconductor integrated circuit device according to claim 13, further comprising a step of:
(n) after said step (i), introducing impurities into said semiconductor substrate to control threshold voltage of a MISFET.
22. A method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein said second silicon oxide film has a thickness larger than that of said first silicon oxide film.
23. A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a first insulating film over a semiconductor substrate;
(b) forming an oxidation resistant film over said first insulating film;
(c) selectively exposing said semiconductor substrate by etching said oxidation resistant film and said first insulating film, wherein said semiconductor substrate is over-etched at said step (c);
(d) forming a second insulating film over said semiconductor substrate exposed after said step (c), wherein said second insulating film extends inward from an end portion of said oxidation resistant film, and wherein an inwardly extended second silicon oxide film is formed on an etched surface of the semiconductor substrate including a silicon surface, extending from adjacent an edge of said first insulating film and under said oxidation resistant film;
(e) forming an inclined surface in said semiconductor substrate by etching said second insulating film, wherein an edge of said inclined surface extends inwardly from the end portion of said oxidation resistant film;
(f) etching said semiconductor substrate to form a trench, using said oxidation resistant film as a mask;
(g) rounding a first boundary portion between said inclined surface and a surface of said semiconductor substrate, and a second boundary portion between said inclined surface and a sidewall of said trench; and
(h) burying a third insulating film in said trench.
24. A method of manufacturing a semiconductor integrated circuit device according to claim 23, further comprising a step of:
(i) between said steps (c) and (d), recessing an end of said first insulating film inward more than an end of said oxidation resistant film.
25. A method of manufacturing a semiconductor integrated circuit device according to claim 23, further comprising a step of:
(j) between said steps (f) and (g), washing said substrate.
26. A method of manufacturing a semiconductor integrated circuit device according to claim 23, wherein a method of thermal oxidation is used for said step (g).
27. A method of manufacturing a semiconductor integrated circuit device according to claim 23, wherein at said step (g), a fourth silicon oxide film is formed over an inner wall of said trench.
28. A method of manufacturing a semiconductor integrated circuit device according to claim 27, further comprising a step of forming a silicon nitride film over said inner wall of said trench.
29. A method of manufacturing a semiconductor integrated circuit device according to claim 23, wherein said step (h) comprises steps of:
(k) forming an insulating film over said oxidation resistant film and inside said trench; and
(l) polishing said insulating film by a CMP method.
30. A method of manufacturing a semiconductor integrated circuit device according to claim 29, wherein at said step (l), said oxidation resistant film is used as an etching stopper.
31. A method of manufacturing a semiconductor integrated circuit device according to claim 29, further comprising a step of:
(m) after said step (k), annealing said insulating film formed in step (k).
32. A method of manufacturing a semiconductor integrated circuit device according to claim 23, further comprising a step of:
(n) after said step (h), introducing impurities into said semiconductor substrate to control threshold voltage of a MISFET.
33. A method of manufacturing a semiconductor integrated circuit device according to claim 23, wherein said second insulating film has a thickness larger than that of said first insulating film.
34. A method of manufacturing a semiconductor integrated circuit device according to claim 23, wherein the over-etching of the semiconductor substrate at the step (c) is an amount of about 10 to 30 nm.
35. A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a first insulating film over a semiconductor substrate;
(b) forming an oxidation resistant film over said first insulating film;
(c) selectively etching said oxidation resistant film and said first insulating film, wherein said semiconductor substrate is over-etched at said step (c);
(d) forming bird’s beaks in said semiconductor substrate by a thermal oxidation method, wherein said bird’s beaks extend under said oxidation resistant film, by oxidizing a silicon surface adjacent an edge of said first insulating film and extending under said oxidation resistant film;
(e) forming an inclined surface in said semiconductor substrate by removing said bird’s beaks, wherein an edge of said inclined surface extends inwardly from an end of said oxidation resistant film;
(f) etching said semiconductor substrate to form a trench after step (e), using said oxidation resistant film as a mask;
(g) rounding a first boundary portion between said inclined surface and a surface of said semiconductor substrate, and a second boundary portion between said inclined surface and a sidewall of said trench; and
(h) burying a third insulating film in said trench.
36. A method of manufacturing a semiconductor integrated circuit device according to claim 35, further comprising a step of:
(i) between said steps (c) and (d), recessing an end of said first insulating film inward more than an end of said oxidation resistant film.
37. A method of manufacturing a semiconductor integrated circuit device according to claim 35, further comprising a step of:
(j) between said steps (f) and (g), washing said substrate.
38. A method of manufacturing a semiconductor integrated circuit device according to claim 35, wherein a method of thermal oxidation is used for said step (g).
39. A method of manufacturing a semiconductor integrated circuit device according to claim 35, wherein at said step (g), a fourth silicon oxide film is formed over an inner wall of said trench.
40. A method of manufacturing a semiconductor integrated circuit device according to claim 39, further comprising a step of forming a silicon nitride film over said inner wall of said trench.
41. A method of manufacturing a semiconductor integrated circuit device according to claim 35, wherein said step (h) comprises steps of:
(k) forming an insulating film over said oxidation resistant film and inside said trench; and
(l) polishing said insulating film by a CMP method.
42. A method of manufacturing a semiconductor integrated circuit device according to claim 41, wherein at said step (l), said oxidation resistant film is used as an etching stopper.
43. A method of manufacturing a semiconductor integrated circuit device according to claim 41, further comprising a step of:
(m) after said step (k), annealing said insulating film formed in said step (k).
44. A method of manufacturing a semiconductor integrated circuit device according to claim 35, further comprising a step of:
(n) after said step (h), introducing impurities into said semiconductor substrate to control threshold voltage of a MISFET.
45. A method of manufacturing a semiconductor integrated circuit device according to claim 35, wherein in step (d) a second insulating film is formed, and said second insulating film has a thickness larger than that of said first insulating film.
46. A method of manufacturing a semiconductor integrated circuit device according to claim 35, wherein the over-etching of the semiconductor substrate at the step (c) is an amount of about 10 to 30 nm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A liquid lens system comprising:
a liquid lens
a logic interface for receiving liquid lens focusing signals from an external processor;
an output peak regulation circuit coupled to the logic interface for receiving the liquid lens focusing signals from the logic interface;
a controllable charge pump for boosting the voltage of a power supply to the liquid lens focusing voltage responsive to the control of the output peak regulation circuit, the charge pump having a first charge pump and a plurality of cascaded second charge pumps, the first charge pump pumping from a voltage difference between an input power supply and a circuit ground, and the plurality of cascaded second charge pumps pumping between a voltage difference equal to the output of the first charge pump and the circuit ground;
an oscillator;
an H-bridge circuit coupled to an output of the controllable charge pump and driven by the oscillator circuit for providing a balanced wave to the liquid lens responsive to the output of the controllable charge pump.
2. The system of claim 1 wherein the driver comprises an integrated circuit.
3. The system of claim 1 wherein the oscillator frequency is a fixed frequency.
4. The system of claim 1 wherein the oscillator frequency is programmable by programming signals received through the logic interface.
5. The system of claim 1 wherein the controllable charge pump is controlled by switching the charge pump on and off.
6. The system of claim 1 wherein the output peak regulation circuit comprises a DAC, a voltage divider and a comparator, wherein the DAC converts a multiple bit liquid lens focusing signal from the logic interface to an analog signal as a first input of the comparator, the voltage divider dividing down the output of the controllable charge pump as a second input to the comparator, the output of the comparator turning the charge pump on and off to maintain an equality between the first and second inputs to the comparator.
7. A liquid lens system comprising:
a liquid lens
a logic interface for receiving liquid lens focusing signals from an external processor;
an output peak regulation circuit coupled to the logic interface for receiving the liquid lens focusing signals from the logic interface;
a charge pump for boosting the voltage of a power supply to a liquid lens focusing voltage responsive to the control of the output peak regulation circuit, the charge pump having a first charge pump and a plurality of second charge pumps, the first charge pump pumping from a voltage difference between an input power supply and a circuit ground, and the plurality of cascaded second charge pumps pumping between a voltage difference equal to the output of the first charge pump and the circuit ground;
the output peak regulation circuit having a DAC, a voltage divider and a comparator, wherein the DAC converts a multiple bit liquid lens focusing signal from the logic interface to an analog signal as a first input ofbe comparator, the voltage divider dividing down the output of the charge pump as a second input to the voltage divider, the output of the comparator turning the charge pump on and off to maintain an equality between the first and second inputs to the comparator;
an oscillator;
an H-bridge circuit coupled to an output of the controllable charge pump and driven by the oscillator circuit for providing a balanced wave to the liquid lens responsive to the output of the controllable charge pump.
8. The system of claim 7 wherein the driver comprises an integrated circuit.
9. The system of claim 7 wherein the oscillator frequency is a fixed frequency.
10. The system of claim 7 wherein the oscillator frequency is programmable by programming signals received through the logic interface.
11. A method of driving a liquid lens comprising:
providing a plurality of charge pumps, a first charge pump operating between the voltage source and the circuit ground, the rest of the plurality of charge pumps being cascaded and operating with a voltage difference equal to the voltage difference between an output of the first charge pump and the circuit ground
controlling the charge pump through a digital interface to provide a controlled charge pump output voltage;
coupling the charge pump output to an H-bridge without a discrete high voltage capacitor coupled to the charge pump output;
coupling an output of the H-bridge to a liquid lens; and,
driving the H-bridge with an oscillator to provide an alternating balanced voltage to the liquid lens;
providing digital liquid lens focusing signals to the digital interface to focus the liquid lens responsive to the focusing signals.
12. The method of claim 11 wherein controlling the charge pump through a digital interface to provide a controlled charge pump output voltage comprises coupling the digital interface to a DAC, dividing down the charge pump output and comparing it with an output of the DAC, and using the result of the comparison to turn the charge pump on and off.
13. A driver for a liquid lens comprising:
a logic interface for receiving liquid lens focusing signals from an external processor;
a pulse width modulation circuit coupled to the logic interface for receiving the liquid lens focusing signals from the logic interface;
a charge pump for boosting the voltage of a power supply to a liquid lens focusing voltage, the charge pump having a first charge pump and a plurality of cascaded second charge pumps, the first charge pump pumping from a voltage difference between an input power supply and a circuit ground, and the plurality of cascaded second charge pumps pumping between a voltage difference equal to the output of the first charge pump and the circuit ground;
an oscillator coupled to the pulse width modulation circuit;
an H-bridge circuit coupled to an output of the charge pump and driven by an output of the pulse width modulation circuit for providing a balanced wave to a liquid lens responsive to the output of the pulse width modulation circuit.
14. The driver of claim 13 wherein the driver comprises an integrated circuit.
15. The driver of claim 13 wherein the oscillator frequency is a fixed frequency.
16. The driver of claim 13 wherein the oscillator frequency is programmable by programming signals received through the logic interface.
17. The driver of claim 13 wherein the balanced wave connects the liquid lens to ground between pulses.