1. In a non-volatile capacitor-less 1T DRAM having:
a semiconductor substrate of a first conducting type with a surface;
a first region of a second conductivity type in said substrate on said surface;
a second region of said second conductivity type in said substrate on said surface, spaced apart from said first region;
a body region of said first conductivity type in said substrate between said first region and said second region, said body region bound by said surface, one or more insulating regions and said first and second regions; wherein the improvement comprising:
a floating gate insulated from said surface and positioned between said first region and said second region; and
a control gate capacitively coupled to said floating gate.
2. The DRAM of claim 1 wherein said floating gate is insulated from a first portion of said surface of said body region between said first region and said second region; and
wherein said control gate is positioned adjacent to the floating gate and is insulated from a second portion of said surface of said body region between said first region and said second region, and is capacitively coupled to said floating gate.
3. The DRAM of claim 1 wherein said floating gate is insulated from said surface of said body region and is positioned over the entire surface between said first region and said second region; and
wherein said control gate is insulated from said floating gate and is positioned over said floating gate.
4. The DRAM of claim 2 wherein said floating gate further having a tip near an end adjacent to the control gate.
5. A method of operating a non-volatile capacitor-less 1T DRAM cell having a semiconductor substrate of a first conducting type with a surface; a first region of a second conductivity type in said substrate on said surface; a second region of said second conductivity type in said substrate, spaced apart from said first region; a body region of said first conductivity type in said substrate between said first region and said second region, said body region bound by said surface, one or more insulating regions and said first and second regions; a floating gate insulated from said surface and positioned between said first region and said second region; and a control gate capacitively coupled to said floating gate; wherein said method comprising:
operating said DRAM cell by storing data in said body region; and
storing said data in said body region to said floating gate upon detection of a loss in power.
6. The method of claim 5 further comprising:
restoring the data stored in the floating gate into the body region, upon application of power to said DRAM.
7. The method of claim 5 wherein said floating gate is insulated from a first portion of said surface of said body region between said first region and said second region, and is closer to said second region than to said first region; and wherein said control gate is positioned adjacent to the floating gate and is insulated from a second portion of said surface of said body region between said first region and said second region, and is capacitively coupled to said floating gate, and is closer to said first region than to said second region.
8. The method of claim 7 wherein said storing step comprises
applying a first negative voltage to the body of the substrate;
applying a first voltage to said first region;
applying a second voltage to said second region, said second voltage more positive than said first voltage; and
applying a third voltage to said control gate, said third voltage more positive than said first voltage, wherein said second voltage and third voltage are sufficient to cause electrons to be injected onto the floating gate if holes are stored in the body region.
9. The method of claim 6 wherein said floating gate is insulated from a first portion of said surface of said body region between said first region and said second region, and is closer to said second region than to said first region; and wherein said control gate is positioned adjacent to the floating gate and is insulated from a second portion of said surface of said body region between said first region and said second region, and is capacitively coupled to said floating gate, and is closer to said first region than to said second region.
10. The method of claim 9, wherein said restoring step comprises:
applying a negative voltage to the body;
applying a first voltage to said first region;
applying a second voltage to said second region, said second voltage more positive than said first voltage; and
applying a third voltage to said control gate, wherein said third voltage is a negative voltage.
11. The method of claim 8, further comprising the step of:
initializing said DRAM prior to said operating step, where in said initializing step comprises:
applying a positive voltage to said control gate;
applying a second negative voltage to the body of said substrate.
12. The method of claim 5 wherein said floating gate is insulated from said surface of said body region and is positioned over the entire surface between said first region and said second region; and wherein said control gate is insulated from said floating gate and is positioned over said floating gate.
13. The methods of claim 12 wherein said storing step comprises:
applying a first positive voltage to the control gate; and
applying a first negative voltage to the body of the substrate.
14. The method of claim 6 wherein said floating gate is insulated from said surface of said body region and is positioned over the entire surface between said first region and said second region; and wherein said control gate is insulated from said floating gate and is positioned over said floating gate.
15. The method of claim 14 wherein said restoring step comprises:
applying a second negative voltage said control gate;
applying a third negative voltage to the body of said substrate, wherein said third negative voltage is more negative than said second negative voltage; and
applying a second positive voltage to said second region.
16. The method of claim 13, further comprising the step of:
initializing said DRAM prior to said operating step, said initializing step comprising:
applying a first negative voltage to said control gate;
applying a second negative voltage to the body of said substrate, wherein said first negative voltage is more negative than said second negative voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for estimating contents of a cache by a computer comprising a processor, comprising:
determining, by the processor, table descriptors referenced by a query, wherein each table descriptor identifies one or more tables in a database system, wherein the determining table descriptors referenced by the query comprises:
providing a central lookup table comprising a page count entry corresponding to a table descriptor for each table in the database system;
using a single scan of each page header stored in the cache, determining, by the processor, if a table descriptor from each page header matches any of the table descriptors referenced by the query;
for each table descriptor from the page headers stored in the cache determined to match any of the table descriptors referenced by the query, increasing, by the processor, a page count value corresponding to the matching table descriptor referenced by the querying, wherein the page count value corresponding to the table descriptor for each table in the database is set to an initial value in an intermediate memory, wherein the increasing the page count value corresponding to the matching table descriptor referenced by the query further comprises: updating the corresponding page count value in the central look-up table with the page count values corresponding to the matching table descriptor referenced by the query;
estimating, by the processor, the contents of the cache using the page count values for each table descriptor referenced by the query; and
calculating, by the processor, a cost of a query execution plan for the query using the estimated contents of the cache.
2. The method of claim 1, wherein the determining the table descriptor referenced by the query comprises:
setting a page count for each referenced table descriptor to an initial value.
3. The method of claim 1, wherein the estimating the contents of the cache using the page count values for each table descriptor referenced by the query comprises: retrieving the page count values corresponding to the table descriptors referenced by the query from the central lookup table.
4. The method of claim 1, wherein the database system comprises a plurality of threads, wherein the increasing the page count value corresponding to the matching table descriptor referenced by the query comprises:
providing a hash table for each of the plurality of threads, each hash table comprising a page count entry corresponding to a table descriptor for each table in the database system, each hash table maintained independently by the owning thread;
for each thread of the plurality of threads:
when the thread copies a page of a first table in the database system into the cache, increasing the page count value corresponding to the first table’s table descriptor in the hash table of the thread; and
when the thread removes a page of a second table in the database system from the cache, decreasing the page count value corresponding to the second table’s table descriptor in the hash table of the thread.
5. The method of claim 4,
wherein the estimating the contents of the cache using the page count value for each table descriptor referenced by the query comprises:
retrieving the page count values corresponding to each table descriptor referenced by the query from the hash tables of each thread; and
determining a sum of the retrieved page count values for each table descriptor referenced by the query.
6. A method for estimating contents of a cache by a computer comprising a processor, comprising:
determining table descriptors referenced by a query for one or more tables in a database system, wherein the database system comprises a plurality of threads;
determining a page count value for each referenced table descriptor using a single scan of table descriptors in page headers stored in a cache, comprising:
providing a hash table for each of the plurality of threads, each hash table comprising a page count entry corresponding to a table descriptor for each table in the database system, each hash table maintained independently by the owning thread;
for each thread of the plurality of threads:
when the thread copies a page of a first table in the database system into the cache, increasing the page count value corresponding to the first table’s table descriptor in the hash table of the thread;
when the thread removes a page of a second table in the database system from the cache, decreasing the page count value corresponding to the second table’s table descriptor in the hash table of the thread;
providing a global hash table comprising a global page count entry corresponding to a table descriptor for each table in the database system, wherein for each hash table of the plurality of threads:
determining if the hash table corresponds to a dead thread;
in response to determining that the hash table corresponds to a dead thread, obtaining the page count values in the hash table of the dead thread;
increasing the corresponding global page count values by the obtained page count values; and
removing the hash table of the dead thread from memory; and
estimating the contents of the cache using the determined page count values, comprising:
retrieving the page count values corresponding to each referenced table descriptor from the hash tables of each thread; and
determining a sum of the retrieved page count values for each referenced table descriptor.
7. The method of claim 6, wherein for each referenced table descriptor in the query, the estimating of the contents of the cache using the determine page count values comprises:
retrieving the page count values corresponding to the referenced table descriptor from the hash table of each thread and from the global hash table; and
determining the sum of the retrieved page count values.
8. The method of claim 4, further comprising:
providing a global hash table comprising a global page count entry corresponding to the table descriptor for each table in the database system;
retrieving the page count values corresponding to each table descriptor from the hash tables of each thread;
determining a sum of the retrieved page count values for each table descriptor;
increasing the corresponding global page count value by the determined sum of each table descriptor; and
setting the page count values in the hash tables of each thread to an initial value.
9. A computer readable memory device comprising a computer program product for estimating contents of a cache, the computer program product executed by a processor comprising:
a computer readable memory having computer readable program code embodied therewith, the computer readable program code configured to:
determine table descriptors referenced by a query, wherein each table descriptor identifies one or more tables in a database system;
set a page count value for each referenced table descriptor to an initial value;
provide a central lookup table comprising a page count entry corresponding to a table descriptor for each table in the database system, wherein the page count value corresponding to the table descriptor for each table in the database system is set to the initial value in an intermediate memory, wherein the computer readable program code configured to increase the page count value corresponding to the matching table descriptor referenced by the query is further configured to:
update the corresponding page count value in the central look-up table with the page count values corresponding to the matching table descriptor referenced by the query;
using a single scan of each page header stored in the cache, determine if a table descriptor from each page header matches any of the table descriptors referenced by the query;
for each table descriptor from the page headers stored in the cache determined to match any of the table descriptors referenced by the query, increase a page count value corresponding to the matching table descriptor referenced by the query estimate the contents of the cache using the page count value for each table descriptor referenced by the query; and
calculate a cost of a query execution plan for the query using the estimated contents of the cache.
10. The computer readable program product of claim 9, wherein the database system comprises a plurality of threads, wherein the computer readable program code configured to increase the page count value corresponding to the matching table descriptor referenced by the query is further configured to:
provide a hash table for each of the plurality of threads, each hash table comprising a page count entry corresponding to a table descriptor for each table in the database system, each hash table maintained independently by the owning thread;
for each thread of the plurality of threads:
when the thread copies a page of a first table in the database system into the cache, increase the page count value corresponding to the first table’s table descriptor in the hash table of the thread; and
when the thread removes a page of a second table in the database system from the cache, decrease the page count value corresponding to the second table’s table descriptor in the hash table of the thread.
11. The computer program product of claim 10,
wherein the computer readable program code configured to estimate the contents of the cache using the page count value for each table descriptor referenced by the query is further configured to:
retrieve the page count values corresponding to each table descriptor referenced by the query from the hash tables of each thread; and
determine a sum of the retrieved page count values for each table descriptor referenced by the query.
12. A system, comprising:
database tables, each database table comprising a plurality of pages; and a computer operatively coupled to the database tables, the computer comprising;
a processor;
a cache comprising copies of one or more of the plurality of pages; and
a computer readable memory operatively coupled to the processor and the cache, the computer readable memory having computer readable program code embodied therewith, the computer readable program code configured to:
determine table descriptors referenced by a query, wherein each table descriptor identifies one or more tables of the database tables;
set a page count value for each referenced table descriptor to an initial value:
provide a central lookup table comprising a page count entry corresponding to a table descriptor for each table in the database system, wherein the page count value corresponding to the table descriptor for each table in the database system is set to the initial value in an intermediate memory, wherein the computer readable program code configured to increase the page count value corresponding to the matching table descriptor referenced by the query is further configured to:
update the corresponding page count value in the central look-up table with the page count value corresponding to the matching table descriptor referenced by the query;
using a single scan of each page header stored in the cache, determine if a table descriptor from each page header matches any of the table descriptors referenced by the query;
for each table descriptor from the page headers stored in the cache determined to match any of the table descriptors referenced by the query, increase a page count value corresponding to the matching table descriptor referenced by the query;
estimate contents of the cache using the page count value for each table descriptor referenced by the query; and
calculate a cost of a query execution plan for the query using the estimated contents of the cache.
13. The system of claim 12, further comprising a plurality of threads, wherein the computer readable program code configured to increase the page count value corresponding to the matching table descriptor referenced by the query is further configured to:
provide a hash table for each of the plurality of threads, each hash table comprising a page count entry corresponding to a table descriptor for each table in the database system, each hash table maintained independently by the owning thread;
for each thread of the plurality of threads:
when the thread copies a page of a first table in the database system into the cache, increase the page count value corresponding to the first table’s table descriptor in the hash table of the thread; and
when the thread removes a page of a second table in the database system from the cache, decrease the page count value corresponding to the second table’s table descriptor in the hash table of the thread,
wherein the computer readable program code configured to determine the referenced table descriptors for the one or more tables in the database system is further configured to: determine table descriptors referenced by a query;
wherein for each referenced table descriptor, the computer readable program code configured to estimate the contents of the cache using the determined page count values is further configured to:
retrieve the page count values corresponding to each referenced table descriptor from the hash tables of each thread; and
determine a sum of the retrieved page count values for each referenced table descriptor.
14. A computer readable memory device comprising a computer program product for estimating contents of a cache, the computer program product executed by a processor comprising:
a computer readable memory having computer readable program code embodied therewith, the computer readable program code configured to:
determine table descriptors referenced by a query for one or more tables in a database system, wherein the database system comprises a plurality of threads;
determine a page count value for each referenced table descriptor using a single scan of table descriptors in page headers stored in a cache, configured to:
provide a hash table for each of the plurality of threads, each hash table comprising a page count entry corresponding to a table descriptor for each table in the database system, each hash table maintained independently by the owning thread;
for each thread of the plurality of threads:
when the thread copies a page of a first table in the database system into the cache, increase the page count value corresponding to the first table’s table descriptor in the hash table of the thread;
when the thread removes a page of a second table in the database system from the cache, decrease the page count value corresponding to the second table’s table descriptor in the hash table of the thread;
provide a global hash table comprising a global page count entry corresponding to a table descriptor for each table in the database system, wherein for each hash table of the plurality of threads:
determine if the hash table corresponds to a dead thread;
in response to determining that the hash table corresponds to a dead thread, obtain the page count values in the hash table of the dead thread;
increase the corresponding global page count values by the obtained page count values; and
remove the hash table of the dead thread from memory; and
estimate the contents of the cache using the determined page count values, comprising:
retrieve the page count values corresponding to each referenced table descriptor from the hash tables of each thread; and
determine a sum of the retrieved page count values for each referenced table descriptor.
15. A system, comprising:
database tables, each database table comprising a plurality of pages; and
a computer operatively coupled to the database tables, the computer comprising:
a processor;
a cache comprising copies of one or more of the plurality of pages; and
a computer readable memory operatively coupled to the processor and the cache, the computer readable memory having computer readable program code embodied therewith, the computer readable program code configured to:
determine table descriptors referenced by a query for one or more tables in a database system, wherein the database system comprises a plurality of threads;
determine a page count value for each referenced table descriptor using a single scan of table descriptors in page headers stored in a cache, configured to:
provide a hash table for each of the plurality of threads, each hash table comprising a page count entry corresponding to a table descriptor for each table in the database system, each hash table maintained independently by the owning thread;
for each thread of the plurality of threads:
\u2003when the thread copies a page of a first table in the database system into the cache, increase the page count value corresponding to the first table’s table descriptor in the hash table of the thread;
\u2003when the thread removes a page of a second table in the database system from the cache, decrease the page count value corresponding to the second table’s table descriptor in the hash table of the thread;
provide a global hash table comprising a global page count entry corresponding to a table descriptor for each table in the database system,
wherein for each hash table of the plurality of threads:
\u2003determine if the hash table corresponds to a dead thread;
\u2003in response to determining that the hash table corresponds to a dead thread, obtain the page count values in the hash table of the dead thread;
\u2003increase the corresponding global page count values by the obtained page count values; and
\u2003remove the hash table of the dead thread from memory; and
estimate the contents of the cache using the determined page count values, comprising:
retrieve the page count values corresponding to each referenced table descriptor from the hash tables of each thread; and
determine a sum of the retrieved page count values for each referenced table descriptor.