1460756993-28234110-c499-4726-b61e-69c93d4f0ee3

1. A pyrolysis reactor for processing waste, comprising:
a reactor chamber;
a source of microwave energy, wherein the reactor chamber comprises a material which is operable to produce a plasma in the presence of the microwave energy.
2. A pyrolysis reactor as claimed in claim 1 wherein the source of microwave energy is a magnetron.
3. A pyrolysis reactor as claimed in claim 2 wherein the magnetron is directly coupled to the reactor chamber.
4. A pyrolysis reactor as claimed in claim 1 wherein the material which is operable to produce a plasma is provided in the form of one or more rods projecting from an interior surface of the reactor chamber.
5. A pyrolysis reactor as claimed in claim 1 wherein the material which is operable to produce a plasma is one of: a metal; boron; and carbon.
6. A pyrolysis reactor as claimed in claim 1 wherein the reactor chamber is provided with a lid which is operable to provide a substantially airtight seal to the interior of the reactor chamber.
7. A pyrolysis reactor as claimed in claim 1, operable to produce varying proportion of solid, liquid or gas by-products in accordance with predetermined operating parameters.
8. A pyrolysis reactor as claimed in claim 1 wherein the source of microwave energy is tuneable in the range: 896 MHz to 5.8 GHz.
9. A method of processing waste comprising the steps of:
supplying waste to a pyrolysis reactor provided with a means for producing a plasma in the presence of microwave energy;
applying microwave energy to the reactor to pyrolyse the waste.
10. The method as claimed in claim 9 wherein the waste is either provided in a batch or via a continuous stream.
11. The method of claim 10 wherein if the waste is provided via a continuous stream, then a conveyor belt is used and the microwave energy is provided via a horn antenna.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A current mirror circuit comprising:
a first transistor having a first electrode connected to a first potential, a second electrode connected to a second potential lower than the first potential, and a third electrode connected to a third potential higher than the second potential;
a second transistor having a first electrode connected to the first potential and the first electrode of the first transistor, a second electrode connected to the second potential, and a third electrode;
an operational amplifier having a high-potential input terminal connected to the third potential and the third electrode of the first transistor, and a low-potential input terminal connected to the third electrode of the second transistor; and
a third transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the third electrode of the second transistor, and a third electrode used as an output terminal and wherein the first and second transistors are operating in a linear region.
2. The circuit according to claim 1, wherein the first to third transistors are each an NMOS transistor.
3. The circuit according to claim 1, wherein the first to third transistors are each a PMOS transistor.
4. The circuit according to claim 1, wherein the first to third electrodes of at least one transistor are gate, source and drain electrodes, respectively.
5. The circuit according to claim 1, wherein the first potential is a reference potential, the second potential is a ground potential, and the third potential is a power supply potential.
6. The circuit according to claim 1, wherein a potential of a connection node of the high-potential input terminal of the operational amplifier with the third electrode of the first transistor is set to a value equal to a potential of a connection node of the low-potential input terminal of the operational amplifier with the third electrode of the second transistor and the second electrode of the third transistor.
7. The circuit according to claim 1, wherein the operational amplifier controls a voltage value of the first electrode of the third transistor to equalize a voltage value of the third electrode of the first transistor to a voltage value of the third electrode of the second transistor.