1. A method of determining the cleaning interval for the interior walls of an RF-powered plasma processing chamber subject to unwanted material build-up, the method comprising:
(a) after cleaning the walls, running a given baseline plasma process on the chamber and determining the corresponding magnitude of a characteristic of the delivered RF power at the fundamental frequency,
(b) repeating step (a) at intervals between production runs, and
(c) cleaning the walls at a time which is a function of the said magnitude.
2. A method as claimed in claim 1, wherein the walls are cleaned when the said magnitude reaches a predetermined threshold level.
3. A method as claimed in claim 1, further including establishing a trend line for changes in the said magnitude over time, the walls being cleaned at a time indicated by the trend line crossing a predetermined threshold level.
4. A method as claimed in claim 1, 2 or 3, wherein the baseline process uses a gas plasma inert to the built-up material.
5. A method as claimed in any preceding claim, wherein the built-up material comprises a polymer resulting from use of the plasma chamber during the said production runs as an etch chamber using polymer-forming chemistry.
6. A method as claimed in any preceding claim, wherein the characteristic of the delivered RF power at the fundamental frequency is the phase.
7. A method as claimed in any preceding claim, wherein the baseline recipe is carried out on a test substrate.
8. A method as claimed in any one of claims 1 to 6, wherein the baseline process is run in the absence of a substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and
a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.
2. The semiconductor device according to claim 1, further comprising:
a storage element provided on the second surface of the semiconductor substrate with an insulating layer in between,
wherein a first end of the contact plug is connected to the storage element.
3. The semiconductor device according to claim 2, wherein the storage element is a spin transfer torque-magnetic tunnel junction storage element (STT-MTJ element).
4. The semiconductor device according to claim 2, wherein
the transistor includes
a pair of diffusion layers configuring a part of the semiconductor substrate,
a source electrode and a drain electrode connected to the respective diffusion layers, and
a gate electrode, and
the gate electrode, the source electrode, or the drain electrode is connected to a second end of the contact plug.
5. The semiconductor device according to claim 2, wherein a periphery of the contact plug is covered with a part of the insulating layer, and the contact plug and the semiconductor substrate are isolated from each other.
6. The semiconductor device according to claim 5, wherein
the semiconductor substrate includes an opening in a part of the isolation region,
the insulating layer is connected to the element isolation layer through the opening of the semiconductor substrate, and
the contact plug passes through a connection portion between the insulating layer and the element isolation layer.
7. The semiconductor device according to claim 1, wherein an occupancy area of the contact plug increases from the first surface toward the second surface.
8. The semiconductor device according to claim 2, wherein
the semiconductor substrate includes a laminate configuration including a first semiconductor layer, a buried oxide film, and a second semiconductor layer, the first semiconductor layer being provided in the element region, the buried oxide film with which the first semiconductor layer is covered, and the second semiconductor layer with which both the buried oxide film and the element isolation layer are covered, and
a periphery of the contact plug is covered with a part of the insulating layer, and the contact plug and the second semiconductor layer are isolated from each other.
9. The semiconductor device according to claim 2, wherein
the semiconductor substrate includes, in the element region, a buried oxide film with which the transistor is covered, and
both the buried oxide film and the element isolation layer are covered with the insulating layer.
10. The semiconductor device according to claim 6, wherein
the transistor includes a fin extending in a first direction, a gate wiring line extending in a second direction, a source wiring line, and a drain wiring line, the gate wiring line with which surfaces other than a back surface of the fin are covered, and
the source wiring line or the drain wiring line is connected to a second end of the contact plug.
11. The semiconductor device according to claim 2, wherein
the transistor includes a fin extending in a first direction, a gate wiring line extending in a second direction, a source wiring line, and a drain wiring line, the gate wiring line with which surfaces other than a back surface of the fin are covered, and
the semiconductor substrate includes a laminate configuration including a buried oxide film and a semiconductor layer, the buried oxide film with which back surfaces of the fin, the gate wiring line, the source wiring line, and the drain wiring line are covered, and the semiconductor layer with which both the buried oxide film and the element isolation layer are covered, and
a periphery of the contact plug is covered with a part of the insulating layer, and the contact plug and the semiconductor layer are isolated from each other.
12. A semiconductor device comprising:
an element formation layer in which a transistor is formed, the transistor including a fin extending in a first direction, a gate wiring line extending in a second direction, a source wiring line, and a drain wiring line, the gate wiring line with which surfaces other than a back surface of the fin are covered;
a buried oxide film with which the transistor is covered;
an insulating layer with which the buried oxide film is covered; and
a contact plug passing through a region other than a region where the transistor is formed of the element formation layer.
13. The semiconductor device according to claim 5, wherein the part with which the periphery of the contact plug is covered of the insulating layer is made of a material having a lower dielectric constant than SiO2.
14. The semiconductor device according to claim 1, wherein an occupancy area of the contact plug decreases from the first surface toward the second surface.
15. The semiconductor device according to claim 1, wherein the contact plug is configured by connecting a portion with an occupancy area decreasing from the first surface toward the second surface and a portion with an occupancy area decreasing from the second surface toward the first surface.
16. The semiconductor device according to claim 4, wherein
a wiring line is included, the wiring line extending from the element region to the isolation region to come into contact with the first surface of the semiconductor substrate, and
the source electrode or the drain electrode and the second end of the contact plug are connected to each other through the wiring line.
17. The semiconductor device according to claim 1, further comprising a wiring configuration in which a plurality of wiring layers are laminated on the second surface of the semiconductor substrate,
wherein a first end of the contact plug is connected to one of the wiring layers in the wiring configuration.
18. A method of manufacturing a semiconductor device comprising:
preparing a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and
forming a contact plug by forming a through hole from the second surface to the first surface in the isolation region and then filling the through hole with a metal material.
19. The method of manufacturing the semiconductor device according to claim 18, wherein
an insulating layer is formed after an opening is formed in the semiconductor substrate, the insulating layer with which the semiconductor substrate is covered, and a part of the insulating layer being in contact with the element insulation layer through the opening, and
the through hole is formed in a portion where the element isolation layer and the insulating layer are connected to each other.
20. The method of manufacturing the semiconductor device according to claim 18, wherein the through hole is obtained by digging the element isolation layer from the first surface to pass through the element isolation layer.
21. The method of manufacturing the semiconductor device according to claim 18, wherein the through hole is obtained by excavating the element isolation layer from the first surface to leave a part of the element isolation layer, and then excavating and removing the remaining part of the element isolation layer from the second surface.
22. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface that face each other, and having a first region, a second region, and a third region, the first region including a transistor in the first surface, the second region including an element isolation layer surrounding the first region in the first surface, and the third region isolated from the first region by the second region,
wherein a first conductive semiconductor portion is provided in the first region,
a second conductive semiconductor portion is provided in the third region, and
an insulating layer is provided in the second region, the insulating layer being sandwiched between the first conductive semiconductor portion and the second conductive semiconductor portion in the second surface.
23. The semiconductor device according to claim 22, wherein the element isolation layer and the insulating layer are in contact with each other in the second region.
24. The semiconductor device according to claim 23, further comprising a contact plug extending from the first surface to the second surface in the second region to pass through the element isolation layer and the insulating layer.
25. The semiconductor device according to claim 22, wherein the element isolation layer and the insulating layer are isolated from each other in the second region.
26. The semiconductor device according to claim 22, wherein the second region includes a portion where the element isolation layer and the insulating layer are in contact with each other and a portion where the element isolation layer and the insulating layer are isolated from each other.
27. The semiconductor device according to claim 22, wherein the insulating layer includes a trench in the second region.
28. The semiconductor device according to claim 22, wherein
a first insulating film and a second insulating film are included, the first insulating film with which the first conductive semiconductor portion is covered, and the second insulating film with which the second conductive semiconductor portion is covered,
the first insulating film is a first band-structure modulation film functioning to limit trapping of free electrons in proximity to a valence band by shifting upward an energy band of the first conductive semiconductor portion, and
the second insulating film is a second band-structure modulation film functioning to limit trapping of free electrons in proximity to a conduction band by shifting downward an energy band of the second conductive semiconductor portion.
29. The semiconductor device according to claim 28, wherein
the first insulating film is made of a high-dielectric constant material having a positive flat band, and
the second insulating film is made of a high-dielectric constant material having a negative flat band.
30. The semiconductor device according to claim 29, wherein the high-dielectric constant material having the positive flat band is Al2O3, HfO2, TiO2, ZrO2, MgO, or an oxide or an oxynitride including Al, Hf, Ti, Zr or Mg.
31. The semiconductor device according to claim 29, wherein the high-dielectric constant material having the negative flat band is Y2O3, La2O3, OeO2, Lu2O3, or SrO.
32. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation, the element region including a transistor region in the first surface, and the isolation region including, in the first surface, an element isolation layer surrounding the element region;
a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate;
a block layer provided to stride across a boundary between the element region and the isolation region in the first surface; and
a wiring line with which the block layer is covered in the first surface and that connects the contact plug and the transistor to each other.
33. The semiconductor device according to claim 32, wherein the block layer is provided to stride across a boundary between a diffusion region of the transistor and the element isolation layer.
34. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including, in the first surface, an element isolation layer surrounding the element region;
a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate; and
a metal layer provided to stride across a boundary between the element region and the isolation region in the first surface and to connect the contact plug and the transistor to each other.
35. A semiconductor unit provided with a semiconductor device and an image pickup device laminated on the semiconductor device, the semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and
a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.
36. The semiconductor unit according to claim 35, wherein
the semiconductor device includes a first wiring line as an uppermost layer thereof,
the image pickup device includes a second wiring line as a lowermost layer thereof, and
the semiconductor device and the image pickup device are laminated to allow the first wiring line and the second wiring line to come into direct contact with each other.
37. The semiconductor unit according to claim 35, wherein
the semiconductor device includes a first wiring line as an uppermost layer thereof,
the image pickup device includes a second wiring line as an uppermost layer or an intermediate layer thereof, and
the first wiring line and the second wiring line are connected to each other through a connection section passing through the image pickup device in a thickness direction.