1. An eyeglass device, comprising:
a lens unit; and
a pair of temple pieces connected to said lens unit, each of said temple pieces including a rigid upper portion and a soft lower portion, said rigid upper portion having a rigid front end connected to said lens unit, and a rigid rear end, said soft lower portion having a front soft section disposed below and connected to said rigid front end, a rear soft section connected to said rigid rear end, and an intermediate soft section disposed between said front and rear soft sections and below said rigid upper portion, said intermediate soft section and said rigid upper portion cooperatively defining an elongate gap therebetween, said soft lower portion having a bottom abutment face extending from said front soft section to said rear soft section for contacting an ear of a user.
2. The eyeglass device of claim 1, wherein said rigid upper portion has a rigid main segment having said rigid front end, and a rigid tail segment having said rigid rear end and including a projection, said rear soft section enclosing said rigid tail segment, said projection extending outwardly of said rear soft section.
3. The eyeglass device of claim 2, wherein said rigid main segment of said rigid upper portion of each of said temple pieces further has a bottom surface, an inner surface facing the other one of said temple pieces, an indented part formed in said inner surface adjacent to said bottom surface, a non-indented part that is formed in said inner surface and that has front, lateral and rear edges bounding said indented part, and a tongue protruding frontwardly into said indented part from said rear edge of said non-indented part, and a groove formed between said tongue and said lateral edge of said non-intended part and defined by a substantially V-shaped wall, said front soft section enclosing said bottom surface and said indented part and having a finger portion engaging said groove.
4. The eyeglass device of claim 2, wherein said rigid main segment of said rigid upper portion of each of said temple pieces further has a bottom surface, an inner surface facing the other one of said temple pieces, an indented part formed in said inner surface adjacent to said bottom surface, a non-indented part that is formed in said inner surface and that has front, lateral and rear edges bounding said indented part, and a protrusion formed in and protruding from said indented part, said front soft section enclosing said bottom surface, said indented part and said protrusion.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A process compensation circuit for an inverting element of a CMOS device, comprising:
a duplicate inverting element connected in parallel with the inverting element of the CMOS device; and
an upside-down inverter stage having an input thereto connected to the output of said duplicate inverting element, and an output thereof connected to the output of said inverting element of the CMOS device;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.
2. The process compensation circuit of claim 1, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate inverting element, said NFET having a source coupled to a logic high voltage supply terminal of the CMOS device;
a PFET having a gate coupled to the output of said duplicate inverting element, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS device; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
3. The process compensation circuit of claim 2, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of the inverting element of the CMOS device.
4. A process compensation device for a CMOS receiver having a NAND stage and an inverter stage; comprising:
a duplicate NAND gate stage connected in parallel with the NAND gate stage of the CMOS receiver; and
an upside-down inverter stage having an input connected to the output of said duplicate NAND gate stage, and an output connected to the output of said NAND stage of the CMOS receiver;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of the output of the NAND gate stage of the CMOS device receiver in the event of a process skew between NFET and PFET devices.
5. The process compensation device of claim 4, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate NAND stage, said NFET having a source coupled to a first logic high voltage supply terminal of the CMOS receiver;
a PFET having a gate coupled to the output of said duplicate NAND stage, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS receiver; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
6. The compensation circuit of claim 5, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of the NAND stage of the CMOS receiver.
7. A CMOS receiver device, comprising:
an input NAND stage operating at a first voltage level, said input NAND stage having a data input and an enable input connected thereto;
an output inverter stage operating at a second voltage level, said output inverter stage having an input connected to an output of said input NAND stage, which defines an intermediate node;
a hysteresis latch coupled to said intermediate node, said hysteresis latch comprising a pair of inverter stages; and
a process compensation circuit coupled in parallel with said input NAND stage, said process compensation circuit further comprising a duplicate NAND stage receiving said data input and said enable input, and an upside-down inverter stage having an input coupled to an output of said duplicate NAND stage and an output connected to said intermediate node;
wherein said upside-down inverter stage is configured to counteract a delayed logic transition of said output of said input NAND stage in the event of a process skew between NFET and PFET devices.
8. The CMOS receiver device of claim 7, wherein said upside-down inverter stage further comprises:
an NFET having a gate coupled to the output of said duplicate NAND stage, said NFET having a source coupled to a logic high voltage supply terminal of the CMOS receiver corresponding to said first voltage level;
a PFET having a gate coupled to the output of said duplicate NAND stage, said PFET having a source coupled to a logic low voltage supply terminal of the CMOS receiver; and
a drain of said NFET coupled to a drain of said PFET, which defines said output of said upside-down inverter stage.
9. The CMOS receiver device of claim 8, wherein said NFET and said PFET of said upside-down inverter stage are formed at a size about 10 times smaller with respect to NFET and PFET devices of said input NAND stage.