1. A system for treating skin, the system comprising:
a handpiece assembly comprising a tip and a main body portion, the main body portion comprising an interior cavity; and
a first canister configured to store at least one treatment material;
a second canister configured to store waste material;
wherein the treatment material and the waste material are in fluid communication with the tip.
2. The system of claim 1, further comprising a fluid transfer device for transferring the treatment material to the tip and the waste material to the canister.
3. The system of claim 1, further comprising a conduit configured to place the first and second canisters in fluid communication with the tip.
4. The system of claim 3, wherein the conduit is routed within the interior cavity of the main body portion.
5. The system of claim 3, wherein the conduit comprises at least two passages, each passage configured to transfer a different material to the tip.
6. The system of claim 1, wherein the handpiece assembly and the first and second canisters form a generally unitary structure.
7. The system of claim 1, wherein the handpiece assembly and at least one of the first and second canisters are substantially separated.
8. The system of claim 1, wherein the first canister comprises at least one compartment, the compartment configured to contain a treatment fluid.
9. The system of claim 8, wherein the treatment fluid comprises a serum.
10. The system of claim 1, wherein the tip is removable.
11. The system of claim 9, wherein the serum comprises an anti-oxidant
12. The system of claim 9, wherein the serum comprises hyaluronic acid.
13. The system of claim 8, wherein the treatment fluid is configured to assist in skin exfoliation.
14. The system of claim 8, wherein the treatment fluid is configured to help hydrate skin.
15. The system of claim 8, wherein the treatment fluid is configured to help reduce sun damage to skin.
16. The system of claim 8, wherein the treatment fluid is configured to help reduce oily skin.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A skew signal generation circuit, comprising:
a pad connected to an external resistor;
a code generator configured to compare a voltage of the pad with a reference voltage to generate a plurality of codes;
a skew signal extractor configured to extract a skew signal from the codes generated by the code generator, the skew signal containing information about a current characteristic of a MOS transistor; and
a driver configured to calibrate a drivability in response to the skew signal.
2. The skew signal generation circuit of claim 1, wherein the codes vary according to the current characteristic of the MOS transistor.
3. The skew signal generation circuit of claim 1, wherein the code generator comprises:
a comparator configured to compare the voltage of the pad with the reference voltage; and
a counter configured to perform a counting operation in response to an output signal of the comparator and generate the plurality of codes.
4. The skew signal generation circuit of claim 1, wherein the skew signal extractor extracts the skew signal by selecting first and second codes from the plurality of codes.
5. The skew signal generation circuit of claim 4, wherein the skew signal extractor comprises:
a first logic element configured to perform a first logic operation on the first and second codes to generate a first skew signal;
a second logic element configured to perform a second logic operation on an inverted signal of the first code and the second code to generate a second skew signal; and
a third logic element configured to perform a third logic operation on the first and second codes to generate a third skew signal.
6. The skew signal generation circuit of claim 5, wherein the first logic element performs a NOR operation, the second logic element performs a NOR operation, and the third logic element performs an AND operation.
7. A semiconductor memory device, comprising:
an impedance calibrator configured to calibrate an output impedance;
a skew signal extractor configured to extract a skew signal containing information about a current characteristic of a transistor in the impedance calibrator; and
an input buffer configured to control an output timing of an input signal in response to the skew signal.
8. The semiconductor memory device of claim 7, wherein the impedance calibrator comprises:
a code generation unit configured to compare a reference voltage with a voltage of a pad connected to an external resistor to generate a plurality of codes; and
a driving unit configured to calibrate a drivability in response to the skew signal.
9. The semiconductor memory device of claim 8, wherein the code generation unit comprises:
a comparator configured to compare the reference voltage with the voltage of the pad; and
a counter configured to perform a counting operation in response to an output signal of the comparator and generate the plurality of codes.
10. The semiconductor memory device of claim 7, wherein the skew signal extractor extracts the skew signal by selecting first and second codes from the plurality of codes.
11. The semiconductor memory device of claim 10, wherein the skew signal extractor comprises:
a first logic element configured to perform a first logic operation on the first and second codes to generate a first skew signal;
a second logic element configured to perform a second logic operation on an inverted signal of the first code and the second code to generate a second skew signal; and
a third logic element configured to perform a third logic operation on the first and second codes to generate a third skew signal.
12. The semiconductor memory device of claim 5, wherein the first logic element performs a NOR operation, the second logic element performs a NOR operation, and the third logic element performs an AND operation.
13. The semiconductor memory device of claim 11, wherein the input buffer comprises a delayer configured to control a delay time in response to the first to third skew signals.
14. The semiconductor memory device of claim 13, wherein the delayer comprises:
a first delay unit configured to delay the input signal by a first delay time;
a second delay unit configured to delay the input signal by a second delay time;
a third delay unit configured to delay the input signal by a third delay time;
a first transfer unit configured to transfer an output signal of the first delay unit in response to the first skew signal;
a second transfer unit configured to transfer an output signal of the second delay unit in response to the second skew signal; and
a third transfer unit configured to transfer an output signal of the third delay unit in response to the third skew signal.
15. The semiconductor memory device of claim 14, wherein the first to third delay units comprise inverter chains.
16. The semiconductor memory device of claim 14, wherein the first to third transfer units comprise transfer gates.
17. A semiconductor memory device, comprising:
an impedance calibrator configured to calibrate an output impedance;
a skew signal extractor configured to extract a skew signal containing information about a current characteristic of a transistor in the impedance calibrator; and
an address buffer configured to control an output timing of an input address in response to the skew signal
wherein the address buffer comprises an electrostatic discharge protector receiving the input address to discharge an electrostatic voltage, a receiver buffering an output address of the electrostatic discharge protector and a delayer delaying an output address of the receiver by a predetermined time in response to the skew signal.
18. The semiconductor memory device of claim 17, wherein the impedance calibrator comprises:
a code generation unit configured to compare a reference voltage with a voltage of a pad connected to an external resistor to generate a plurality of codes; and
a driving unit configured to calibrate a drivability in response to the skew signal.
19. The semiconductor memory device of claim 18, wherein the code generation unit comprises:
a comparator configured to compare the reference voltage with the voltage of the pad; and
a counter configured to perform a counting operation in response to an output signal of the comparator and generate the plurality of codes.
20. The semiconductor memory device of claim 17, wherein the skew signal extractor extracts the skew signal by selecting first and second codes from the plurality of codes.
21. The semiconductor memory device of claim 20, wherein the skew signal extractor comprises:
a first logic element configured to perform a first logic operation on the first and second codes to generate a first skew signal;
a second logic element configured to perform a second logic operation on an inverted signal of the first code and the second code to generate a second skew signal; and
a third logic element configured to perform a third logic operation on the first and second codes to generate a third skew signal.
22. The semiconductor memory device of claim 17, wherein the delayer comprises:
a first delay unit configured to delay the input signal by a first delay time;
a second delay unit configured to delay the input signal by a second delay time;
a third delay unit configured to delay the input signal by a third delay time;
a first transfer unit configured to transfer an output signal of the first delay unit in response to the first skew signal;
a second transfer unit configured to transfer an output signal of the second delay unit in response to the second skew signal; and
a third transfer unit configured to transfer an output signal of the third delay unit in response to the third skew signal.