1. A method of maintaining a state of a memory cell without interrupting access to said memory cell, said method comprising:
applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and
accessing the cell.
2. The method of claim 1, wherein said applying comprises applying said back bias to a terminal of said cell that is not used for address selection of said cell.
3. The method of claim 1, wherein said back bias is applied as a constant positive voltage bias.
4. The method of claim 1, wherein said back bias is applied as a periodic pulse of positive voltage.
5. The method of claim 1, wherein a maximum potential that can be stored in said floating body is increased by said applying back bias to the cell, resulting in a relatively larger memory window.
6. The method of claim 1, wherein said application of back bias performs a holding operation on said cell, said method further comprises simultaneously performing a read operation on said cell at the same time that said holding operation is being performed.
7. The method of claim 1, wherein the cell is a multi-level cell, wherein said floating body is configured to indicate more than one state by storing multi-bits, said method further comprising monitoring cell current of said cell to determine a state of said cell.
8. A method of operating a memory array having rows and columns of memory cells assembled into an array of said memory cells, each said memory cell having a floating body region for storing data; the method comprising:
performing a holding operation on at least all of said cells not aligned in a row or column of a selected cell; and
accessing said selected cell and performing a read or write operation on said selected cell while performing said hold operation on said at least all of said cells not aligned in a row or column of said selected cell.
9. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells and wherein said performing a read or write operation comprises performing a read operation on said selected cell.
10. The method of claim 8, wherein said holding operation is performed by applying back bias to a terminal not used for memory address selection.
11. The method of claim 10, wherein said terminal is segmented to allow independent control of the applied hack bias to a selected portion of the memory array.
12. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell, and wherein said performing a read or write operation comprises performing a write \u201c0\u201d operation on said selected cell, wherein a write \u201c0\u201d operation is also performed on all of said cells sharing a common source line terminal with said selected cell during said performing a write\u201c0\u201d operation.
13. The method of claim 8, comprising an individual bit write \u201c0\u201d operation, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell, while said performing a read or write operation comprises performing a write \u201c0\u201d operation on said selected cell.
14. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a write \u201c1\u201d operation on said selected cell.
15. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a multi-level write operation on said selected cell, using an alternating write and verify algorithm.
16. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a multi-level write operation on said selected cell, wherein said multi-level write operation includes: ramping a voltage applied to said selected cell to perform said write operation; reading the state of said selected cell by monitoring a change in current through said selected cell; and removing the ramped voltage applied once the change in cell current reaches a predetermined value.
17. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a multi-level write operation on said selected cell, wherein said multi-level write operation includes: ramping a current applied to said selected cell to perform said write operation; reading the state of said selected cell by monitoring a change in voltage across a bit line and a source line of said selected cell; and removing the ramped current applied once the change in cell voltage reaches a predetermined value.
18. The method of claim 17, wherein said multi-level write operation permits bit-level selection of a bit portion of memory of said selected cell.
19. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a single-level or multi-level write operation on said selected cell, wherein said single-level and each level of said multi-level write operation includes: ramping a voltage applied to said selected cell to perform said write operation; reading the state of said selected cell by monitoring a change in current toward an addressable terminal of said selected cell; and verifying a state of said write operation using a reference memory cell.
20. The method of claim 19, further comprising configuring a state of said reference memory cell using a write-then-verify operation, prior to performing said write operation.
21. The method of claim 19, wherein said configuring a state of said reference memory cell comprises configuring said state upon power up of said memory array.
22. A method of operating a memory array having rows and columns of memory cells assembled into an array of said memory cells, each said memory cell having a floating body region for storing data; the method comprising:
refreshing a state of at least one of said memory cells; and
accessing at least one other of said memory cells, wherein access of said at least one other of said memory cells in not interrupted by said refreshing, and wherein said refreshing is performed without alternating read and write operations.
23. The method of claim 22, wherein said at least one of said memory cells is a multi-level memory cell.
24. A method of operating a memory array having rows and columns of memory cells assembled into an array of said memory cells, each said memory cell having a floating body region for storing data; the method comprising:
accessing a selected memory cell from said memory cells; and
performing a simultaneous write and verify operation on said selected memory cell without performing an alternating write and read operation.
25. The method of claim 24, wherein said selected memory cell is a multi-level memory cell.
26. The method of claim 24, wherein a verification portion of said write and verify operation is performed by sensing a current change in the column direction of the array in a column that said selected cell is connected to.
27. The method of claim 24, wherein a verification portion of said write and verify operation is performed by sensing a current change in the row direction of the array in a row that said selected cell is connected to.
28. The method of claim 24, wherein a write portion of said write and verify operation employs use of a drain or gate voltage ramp.
29. The method of claim 24, wherein a write portion of said write and verify operation employs use of a drain current ramp.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An encapsulated buck converter module with an integral capacitor comprising:
a) a low side transistor and a control integrated circuit bonded to a first component attachment section on a first side of a leadframe;
b) a first clip between a source of said low side transistor and a second component attachment section;
c) a source contact of a high side transistor attached to said first component attachment section on a second side of said leadframe with a gate contact of said high side transistor attached to a third component attachment section;
d) a conductive member attached to said first component attachment section and said second component attachment section on said second side of said leadframe wherein said first side of said conductive member attached to said second conductive member forms a highly conductive path with a portion of a second side of said conductive member while any portion of said first side of said conductive member attached to said first component attachment section is insulated from said first side of said conductive member;
e) a first plate of a capacitor attached to a drain contact of said high side transistor and a second plate of said capacitor attached to said second side of said conductive member; and
f) means for forming an external connection to said drain contact of said high side transistor.
2. The encapsulated buck converter module set forth in claim 1 wherein said means for forming an external connection comprises a second clip attached to said drain of said high side transistor.
3. The encapsulated buck converter module set forth in claim 2 wherein said second clip has a substantially 90 degree bend.
4. The encapsulated buck converter module set forth in claim 3 wherein an end of said second clip is not encapsulated and forms said external connection.
5. The encapsulated buck converter module set forth in claim 1 wherein said conductive member is a metal plate which is attached to said first component attachment section by a non-conductive bonding material.
6. The encapsulated buck converter module set forth in claim 1 where said conductive member comprises a first plate bonded to one side of an insulator with second and third plates bonded to an opposite side of said insulator with at least one via electrically connecting said first metal plate to said second metal plate, and said third metal plate is attached only to said first component attachment section and said second plate is attached only to said second component attachment section.
7. The encapsulated buck converter module set forth in claim 1 said first clip has a substantially 90 degree bend wherein a flat portion of a major surface of said first clip is attached to said source of said low side transistor and an end of said first clip is attached to said second component attachment section.
8. The encapsulated buck converter module set forth in claim 1 wherein said first side of said leadframe is closer to a bottom of said encapsulated buck converter module than said second side of said leadframe.
9. The encapsulated buck converter module set forth in claim 1 wherein each of said component attachment sections is integral with an external lead.
10. A method for forming an encapsulated buck converter module with an integral capacitor comprising the steps of:
a) die bonding a low side transistor and a control integrated circuit to first component attachment section on a first side of a leadframe;
b) attaching a first clip between a source of said low side transistor and a second component attachment section;
c) attaching wirebonds to said control integrated circuit, low side transistor and the component attachment sections of leadframe;
d) attaching on a second side of said leadframe a source contact of a high side transistor to said first component attachment section and a gate contact of said high side transistor to a third component attachment section;
e) attaching to said second side of said leadframe a first side of a conductive member to said first component attachment section and said second component attachment section wherein said first side of said conductive member attached to said second conductive member forms a highly conductive path with a portion of a second side of said conductive member while any portion of said first side of said conductive member attached to said first component attachment section is insulated from said first side of said conductive member;
f) attaching a first plate of a capacitor to a drain contact of said high side transistor and a second plate of said capacitor to said second side of said conductive member;
g) attaching a first end of a second clip to said drain contact of said high side transistor; and
h) encapsulating said leadframe is such a manner that part of said leadframe and a second end of said second clip is not encapsulated.
11. The method set forth in claim 10 wherein said conductive member is a metal plate which is attached to said first component attachment section by a non-conductive bonding material.
12. The method set forth in claim 10 where said conductive member comprises a first plate bonded to one side of an insulator with second and third plates bonded to an opposite side of said insulator with at least one via electrically connecting said first metal plate to said second metal plate, and said third metal plate is attached only to said first component attachment section and said second plate is attached only to said second component attachment section.
13. The method set forth in claim 10 said first clip has a substantially 90 degree bend wherein a flat portion of a major surface of said first clip is attached to said source of said low side transistor and an end of said first clip is attached to said second component attachment section.
14. The method set forth in claim 10 wherein said second clip has a substantially 90 degree bend.
15. The method set forth in claim 10 wherein said first side of said leadframe is closer to a bottom of said encapsulated buck converter module than said second side of said leadframe.
16. The method set forth in claim 10 wherein each of said component attachment sections is integral with an external lead.