1. A radiation detection device comprising:
an optical detector pixel array having one or more pixel cells which can be triggered by optical photons;
a timestamp trigger unit in operative communication with at least one timing unit;
wherein the timestamp trigger unit is configured to receive signals from the optical detector pixel array and is further configured to determine at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array;
wherein the at least a first pixel cell triggering rate is determined by computing the number of triggered pixel cells within the optical detector pixel array within a predetermined delay period;
wherein the timestamp trigger unit is configured to cause the at least one timing unit to generate a first timestamp indicative of the end of the predetermined delay period based on the at least a first pixel cell triggering rate for the one or more pixel cells (9) within the optical detector pixel array.
2. A radiation detection device according to claim 1 wherein the timestamp trigger unit is configured to cause the at least one timing unit to generate the first timestamp if the at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array exceeds a threshold rate value.
3. (canceled)
4. A radiation detection device according to claim 1 wherein the first timestamp is generated based further upon a triggered pixel cell count for the one or more pixel cells within the optical detector pixel array;
wherein the first timestamp is generated if the triggered pixel cell count meets a predetermined triggered pixel cell count condition prior to the at least a first pixel cell triggering rate meeting a predetermined pixel cell triggering rate condition.
5. A radiation detection device according to claim 4 wherein the predetermined triggered pixel cell count condition is that the triggered pixel cell count exceeds a threshold count value;
and wherein the predetermined pixel cell triggering rate condition is that the at least a first pixel cell triggering rate exceeds a threshold rate value;
and wherein the predetermined delay period begins when the triggered pixel cell count exceeds the threshold count value;
such that the at least one timing unit is caused to generate the first timestamp if the triggered pixel cell count exceeds the threshold count value and then subsequently exceeds a higher count value before the end of the predetermined delay period such that the threshold rate value is exceeded.
6. A radiation detection device according to claim 4 further comprising a timestamp adjustment unit configured to receive the first timestamp from the at least one timing unit;
wherein the timestamp adjustment unit is configured to generate an adjusted first timestamp indicative of the time at which the predetermined triggered pixel cell count condition was met by subtracting the predetermined delay period from the time of the first timestamp.
7. A radiation detection device according to claim 1 wherein the timestamp trigger unit is configured to cause the at least one timing unit to generate the first timestamp based further on a second pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array and wherein the second pixel cell triggering rate is determined at a later point in time to the first pixel cell triggering rate.
8. A radiation detection device according to claim 7 wherein the timestamp trigger unit is configured to cause the at least one timing unit to generate the first timestamp if the first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array exceeds a first threshold rate and the second pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array exceeds a second threshold rate.
9. A radiation detection device according to claim 1 further comprising at least a second timing unit;
wherein the at least a second timing unit is in communication with the timestamp trigger unit;
wherein the timestamp trigger unit is further configured to cause the at least a second timing unit to generate a photon count timestamp indicative of the time of detection of one or more optical photons by pixel cells within the optical detector pixel array.
10. A radiation detection device according to claim 1 further comprising at least a second timing unit;
wherein the at least a second timing unit is in communication with the timestamp trigger unit;
wherein the timestamp trigger unit is further configured to cause the at least a second timing unit to generate a triggering rate timestamp indicative of the time at which the pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array meets a second triggering rate condition.
11. A PET imaging system comprising a plurality of radiation detection devices according to claim 1;
wherein each radiation detection device further comprises a scintillator element in optical communication with the optical detector pixel array.
12. A PET imaging system comprising a plurality of radiation detection devices according to claim 9;
wherein each radiation detection device further comprises a scintillator element in optical communication with the optical detector pixel array;
the PET imaging system further comprising:
a depth-of-interaction calculation unit;
wherein the depth-of-interaction calculation unit is configured to compute a depth of interaction of a radiation quant in the scintillator element based on either i) the time difference between the first timestamp and the photon count timestamp or ii) the time difference between the first timestamp and the triggering rate timestamp.
13. A PET imaging system comprising a plurality of radiation detection devices according to claim 9;
wherein each radiation detection device further comprises a scintillator element in optical communication with the optical detector pixel array;
the PET imaging system further comprising a timestamp correction unit configured to generate a corrected timestamp based on a weighted average of the first timestamp and the second timestamp.
14. A timing method for use in PET imaging or Cherenkov imaging, the timing method comprising the steps of:
receiving signals from an optical detector pixel array indicative of the triggering of one or more pixel cells within the optical detector pixel array;
determining at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array by computing the number of triggered pixel cells within the optical detector pixel array within a predetermined delay period;
generating a first timestamp that is indicative of the end of the predetermined delay period and is also indicative of the detection of a radiation quant based on the at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array.
15. A computer program product comprising computer executable instructions to perform the method steps of:
receiving signals from an optical detector pixel array indicative of the triggering of one or more pixel cells within the optical detector pixel array;
determining at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array by computing the number of triggered pixel cells within the optical detector pixel array predetermined delay period;
generating a first timestamp that is indicative of the end of the predetermined delay period and is also indicative of the detection of a radiation quant based on the at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array.
16. A computer program product according to claim 15 wherein the computer executable instructions are further configured to perform the method step of:
generating an adjusted first timestamp by subtracting the predetermined delay period from the time of the first timestamp.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
an input terminal,
an output terminal,
a first terminal,
a second terminal,
a third terminal, and
a fourth terminal;
a first transistor for transmitting electric potential of the first terminal to the output terminal;
a second transistor which fixes electric potential of the output terminal by conducting electricity between the output terminal and the second terminal in accordance with electric potential of the fourth terminal; and
a third transistor which fixes electric potential of the third terminal by conducting electricity between the third terminal and the second terminal in accordance with the electric potential of the fourth terminal,
wherein a first pulse is configured to be input from the input terminal, and
wherein a second pulse reversed to the first pulse is configured to be input from the fourth terminal.
2. The semiconductor device according to claim 1, wherein an average of an area of an gate electrode of the second transistor and an area of an gate electrode of the third transistor is larger than an area of an gate electrode of the first_transistor.
3. The semiconductor device according to claim 1, wherein a wiring electrically connected to the second terminal and a wiring electrically connected to the first terminal are provided on a side opposite to the output terminal with respect to the first transistor, the second transistor, and the third transistor.
4. The semiconductor device according to claim 1, further comprising a first wiring layer, a second wiring layer, a third wiring layer, an insulating film, and an interlayer insulating film, and wherein the insulating film is provided between the first wiring layer and the second wiring layer,
wherein the interlayer insulating film is formed between the second wiring layer and the third wiring layer,
wherein the interlayer insulating film is thicker than the insulating film,
wherein a first electrode electrically connected to the first terminal comprises a part of_the second wiring layer,
wherein a second electrode electrically connected to the output terminal comprises at least a part of the first wiring layer and a part of the third wiring layer, and
wherein at a region where the second electrode electrically connected to the output terminal and the first electrode electrically connected to the first terminal are crossed, the second electrode electrically connected to the output terminal comprises a part of the third wiring layer.
5. A display device comprising a semiconductor device according to claim 1, further comprising an external driver circuit, and a connection wiring substrate, wherein the semiconductor device and the external driver circuit are connected to each other with one connection wiring substrate.
6. An electronic device using the display device according to claim 5.
7. A semiconductor device comprising:
an input terminal,
an output terminal,
a first terminal,
a second terminal,
a third terminal,
a fourth terminal, and
a fifth terminal;
a first transistor for transmitting electric potential of the first terminal to the output terminal;
a rectifying element which turns ON the first transistor in accordance with electric potential of the input terminal;
a second transistor which fixes electric potential of the output terminal by conducting electricity between the output terminal and the second terminal in accordance with electric potential of the fifth terminal;
a third transistor which fixes electric potential of the third terminal by conducting electricity between the third terminal and the second terminal in accordance with electric potential of the fourth terminal; and
a circuit which reverses the electric potential of the third terminal and outputs the electric potential to the fifth terminal,
wherein a first pulse is configured to be input from the input terminal, and
wherein a second pulse reversed to the first pulse is configured to be input from the fourth terminal.
8. The semiconductor device according to claim 7, wherein an average of an area of an gate electrode of the second transistor and an area of an gate electrode of the third transistor is larger than an area of an gate electrode of the first_transistor.
9. The semiconductor device according to claim 7, wherein a wiring electrically connected to the second terminal and a wiring electrically connected to the first terminal are provided on a side opposite to the output terminal with respect to the first transistor, the second transistor, and the third transistor.
10. The semiconductor device according to claim 7, further comprising a first wiring layer, a second wiring layer, a third wiring layer, an insulating film, and an interlayer insulating film, and wherein the insulating film is provided between the first wiring layer and the second wiring layer,
wherein the interlayer insulating film is formed between the second wiring layer and the third wiring layer,
wherein the interlayer insulating film is thicker than the insulating film,
wherein a first electrode electrically connected to the first terminal comprises a part of_the second wiring layer,
wherein a second electrode electrically connected to the output terminal comprises at least a part of the first wiring layer and a part of the third wiring layer, and
wherein at a region where the second electrode electrically connected to the output terminal and the first electrode electrically connected to the first terminal are crossed, the second electrode electrically connected to the output terminal comprises a part of the third wiring layer.
11. A display device comprising a semiconductor device according to claim 7, further comprising an external driver circuit, and a connection wiring substrate, wherein the semiconductor device and the external driver circuit are connected to each other with one connection wiring substrate.
12. An electronic device using the display device according to claim 11.
13. A semiconductor device comprising:
an input terminal,
an output terminal,
a first terminal,
a second terminal,
a third terminal,
a fourth terminal,
a fifth terminal, and
a sixth terminal;
a first transistor for transmitting electric potential of the first terminal to the output terminal;
a first rectifying element which turns ON the first transistor in accordance with electric potential of the input terminal;
a second transistor which fixes electric potential of the output terminal by conducting electricity between the output terminal and the second terminal in accordance with electric potential of the fourth terminal;
a third transistor which fixes electric potential of the third terminal by conducting electricity between the third terminal and the second terminal in accordance with the electric potential of the fourth terminal;
a second rectifying element for increasing electric potential of the fifth terminal in accordance with the electric potential of the output terminal; and
a fourth transistor for lowering electric potential of the sixth terminal by conducting electricity between the second terminal and the sixth terminal,
wherein the fourth terminal is electrically connected to one of source and drain of a fifth transistor.
14. The semiconductor device according to claim 13, wherein an average of an area of an gate electrode of the second transistor and an area of an gate electrode of the third transistor is larger than an area of an gate electrode of the first_transistor.
15. The semiconductor device according to claim 13, wherein a wiring electrically connected to the second terminal and a wiring electrically connected to the first terminal are provided on a side opposite to the output terminal with respect to the first transistor, the second transistor, and the third transistor.
16. The semiconductor device according to claim 13, further comprising a first wiring layer, a second wiring layer, a third wiring layer, an insulating film, and an interlayer insulating film, and wherein the insulating film is provided between the first wiring layer and the second wiring layer,
wherein the interlayer insulating film is formed between the second wiring layer and the third wiring layer,
wherein the interlayer insulating film is thicker than the insulating film,
wherein a first electrode electrically connected to the first terminal comprises a part of the second wiring layer,
wherein a second electrode electrically connected to the output terminal comprises at least a part of the first wiring layer and a part of the third wiring layer, and
wherein at a region where the second electrode electrically connected to the output terminal and the first electrode electrically connected to the first terminal are crossed, the second electrode electrically connected to the output terminal comprises a part of the third wiring layer.
17. The display device comprising a semiconductor device according to claim 13, further comprising an external driver circuit, and a connection wiring substrate, wherein the semiconductor device and the external driver circuit are connected to each other with one connection wiring substrate.
18. The electronic device using the display device according to claim 17.
19. The semiconductor device according to claim 13, wherein the first, second, third and fourth transistors have a same polarity.
20. The semiconductor device according to claim 19, further comprising:
a circuit comprising all transistors comprising the first, second, third and fourth transistors,
wherein all the transistors have the same polarity.