1. A liquid crystal display device comprising:
a liquid crystal cell in which a liquid crystal layer is provided between a pair of substrates;
a backlight device provided on a back surface side of the liquid crystal cell;
a first light diffusing layer arranged between the backlight device and the liquid crystal cell;
a first polarizer arranged between the first light diffusing layer and the liquid crystal cell; and
a second light diffusing layer arranged on a front surface side of the liquid crystal cell, wherein
the first light diffusing layer has both or one of a light diffusing function and a light polarizing function, and emergent light from the first light diffusing layer has light distribution characteristics such that a luminance value in a direction of 70 degrees with respect to a normal of a light incidence plane of the liquid crystal cell is 20% or less with respect to a luminance value in the direction of the normal,
the second light diffusing layer is constituted by a second polarizer and a light diffusing membrane provided on a front surface side of the second polarizer, and
the backlight device is divided into a plurality of regions and is capable of controlling luminance per region.
2. The liquid crystal display device according to claim 1, wherein the backlight device comprises LEDs respectively provided in correspondence with the plurality of regions.
3. The liquid crystal display device according to claim 1, wherein the emergent light from the first light diffusing layer includes non-collimated light.
4. The liquid crystal display device according to claim 1, wherein the first light diffusing layer has both a light diffusing function and a light polarizing function.
5. The liquid crystal display device according to claim 4, wherein the first light diffusing layer comprises a light diffusing plate that performs the light diffusing function and a light polarizing structure board that performs the light polarizing function, and the first light diffusing layer is constituted such that the light polarizing structure board is provided on a front surface side of the light diffusing plate.
6. The liquid crystal display device according to claim 1, wherein the liquid crystal cell is one of a TN liquid crystal cell, an IPS liquid crystal cell, and a VA liquid crystal cell.
7. The liquid crystal display device according to claim 1, wherein a retarder is further arranged on a back surface side andor a front surface side of the liquid crystal cell.
8. The liquid crystal display device according to claim 1 which does not comprise a retarder.
9. The liquid crystal display device according to claim 1, wherein the liquid crystal cell is a TN liquid crystal cell and the liquid crystal display device does not comprise a retarder.
10. The liquid crystal display device according to claim 1, wherein the light diffusing membrane has light diffusion characteristics such that a relative intensity of a laser beam emergent in a direction that is inclined by 40 degrees with respect to a normal direction of a back surface of the light diffusing membrane at a position of 280 mm from a front surface of the light diffusing membrane relative to an intensity of a laser beam with a wavelength of 543.5 nm that is incident from the normal direction of the back surface of the light diffusing membrane is 0.0002% or greater.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
providing data for storage in a memory, which comprises multiple analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections; and
storing the data in the memory cells in accordance with a programming order that alternates among the sections, including storing a first portion of the data in a first section, then storing a second portion of the data in a second section different from the first section, and then storing a third portion of the data in the first section.
2. The method according to claim 1, wherein each of the memory cells is capable of storing at least a respective Least Significant Bit (LSB) and a respective Most Significant Bit (MSB), and wherein storing the data comprises, in a given word line, storing the first and second portions in LSBs of the memory cells of the first and second sections, and then storing the third portion in MSBs of the memory cells of the first section.
3. The method according to claim 1, wherein storing the data comprises applying to the memory cells respective sequences of programming and verification iterations.
4. The method according to claim 3, wherein applying the sequences comprises time-interleaving the sequences applied in the first and second sections of a given word line with one another.
5. Apparatus, comprising:
an interface configured to communicate with a memory, which comprises multiple analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections; and
storage circuitry, which is configured to store data in the memory cells in accordance with a programming order that alternates among the sections, including storing a first portion of the data in a first section, then storing a second portion of the data in a second section different from the first section, and then storing a third portion of the data in the first section.
6. The apparatus according to claim 5, wherein each of the memory cells is capable of storing at least a respective Least Significant Bit (LSB) and a respective Most Significant Bit (MSB), and wherein, in a given word line, the storage circuitry is configured to store the first and second portions in LSBs of the memory cells of the first and second sections, and then to store the third portion in MSBs of the memory cells of the first section.
7. The apparatus according to claim 5, wherein the storage circuitry is configured to store the data by applying to the memory cells respective sequences of programming and verification iterations.
8. The apparatus according to claim 7, wherein the storage circuitry is configured to time-interleave the sequences applied in the first and second sections of a given word line with one another.
9. Apparatus, comprising:
a memory comprising multiple analog memory cells, which are arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections; and
storage circuitry, which is configured to store data in the memory cells in accordance with a programming order that alternates among the sections, including storing a first portion of the data in a first section, then storing a second portion of the data in a second section different from the first section, and then storing a third portion of the data in the first section.
10. The apparatus according to claim 9, wherein each of the memory cells is capable of storing at least a respective Least Significant Bit (LSB) and a respective Most Significant Bit (MSB), and wherein, in a given word line, the storage circuitry is configured to store the first and second portions in LSBs of the memory cells of the first and second sections, and then to store the third portion in MSBs of the memory cells of the first section.
11. The apparatus according to claim 9, wherein the storage circuitry is configured to store the data by applying to the memory cells respective sequences of programming and verification iterations.
12. The apparatus according to claim 11, wherein the storage circuitry is configured to time-interleave the sequences applied in the first and second sections of a given word line with one another.