What is claimed is:
1. A disc holding apparatus provided within a main body and provided for holding an information recording disc, comprising:
a holding body protruded from said main body by a supporting line having an elasticity, provided so as to move close to and apart from said main body and engaging with a center hole of said disc in such a manner as to put in and take out with respect to an inner portion of the center hole,
wherein a disc receiving portion for receiving said disc is provided so as to protrude from said main body at a time when said holding body moves close to a side of said main body, in an outer side of said holding body.
2. A disc holding apparatus as claimed in claim 1, wherein said supporting line is provided at a plurality of portions, and at least one of said supporting lines has a strength lower than a strength of the other supporting lines.
3. A disc holding apparatus provided with a main body and provided for holding an information recording disc, comprising:
a holding body protruded from said main body by a supporting line having an elasticity, provided so as to move close to and apart from said main body and engaging with a center hole of said disc in such a manner as to put in and take out with respect to an inner portion of the center hole,
wherein said supporting line is provided at a plurality of portions, and at least one of said supporting lines has a strength lower than a strength of the other supporting lines.
4. A disc holding apparatus as claimed in claim 2 or 3, wherein said supporting line is provided at three portions, three supporting lines extend radially around said holding body in three directions at a substantially uniform interval, and at least one of said supporting lines has a strength lower than a strength of the other two supporting lines.
5. A disc holding apparatus as claimed in claim 2, 3 or 4, wherein said supporting line having the lower strength is structured such that a width or a thickness thereof is smaller than that of the other supporting lines.
6. A disc holding apparatus as claimed in claim 1, 2, 3, 4 or 5, wherein said holding body has a disc holding line protruding outward and having an elasticity, said disc holding line is engaged with an edge portion of the center hole in a side opposite to said main body in a state that said holding body is inserted into the center hole of said disc in such a manner as to freely engage and disengage, and is deformed in such a manner as to be compressed inward when said holding body is pressed so as to move close to said main body, thereby allowing said holding body to pass through said center hole.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method comprising:
issuing a request hint prior to or while identifying whether requested data andor one or more instructions are in a first memory;
accessing a second memory to fetch data andor one or more instructions in response to the request hint;
storing the data andor instruction(s) accessed from the second memory in a buffer; and
if the requested data andor instruction(s) are not in the first memory, returning the data andor instruction(s) from the buffer.
2. The method of claim 1, comprising identifying whether the requested data andor instruction(s) are stored in a write buffer in response to the request hint.
3. The method of claim 1, comprising identifying, prior to issuing the request hint, whether the requested data andor instruction(s) are in a third memory,
wherein the issuing comprises issuing the request hint if the requested data andor instruction(s) are not in the third memory.
4. The method of claim 1, wherein the returning comprises issuing a memory fetch request for the requested data andor instruction(s).
5. The method of claim 4, wherein the returning comprises identifying whether the requested data and instruction(s) are in a write buffer in response to the memory fetch request.
6. An apparatus comprising:
a first memory;
logic coupled to the first memory to issue a request hint prior to or while identifying whether requested data andor one or more instructions are in the first memory, the logic to issue a memory fetch request if the requested data andor instruction(s) are not in the first memory; and
a memory controller coupled to the logic and comprising a buffer, the memory controller to receive the request hint and to access a second memory to fetch data andor one or more instructions in response to the request hint and store the accessed data andor instruction(s) in the buffer, the memory controller to return to the logic the accessed data andor instruction(s) from the buffer in response to the memory fetch request.
7. The apparatus of claim 6, wherein the first memory comprises a primary cache memory.
8. The apparatus of claim 6, wherein the first memory comprises a secondary cache memory.
9. The apparatus of claim 6, comprising a third memory coupled to the logic, the logic to identify whether the requested data andor instruction(s) are in the third memory and to issue the request hint if the requested data andor instruction(s) are not in the third memory.
10. The apparatus of claim 6, wherein the memory controller comprises a write buffer to store data andor instruction(s) to be written to the second memory, the memory controller to identify whether the requested data andor instruction(s) are stored in the write buffer in response to the request hint.
11. The apparatus of claim 6, wherein the memory controller comprises a write buffer to store data andor instruction(s) to be written to the second memory, the memory controller to identify whether the requested data and instruction(s) are stored in the write buffer in response to the memory fetch request.
12. The apparatus of claim 6, wherein the logic comprises instruction processing logic to issue the request hint.
13. The apparatus of claim 6, wherein the logic comprises primary cache control logic to issue the request hint.
14. A system comprising:
main memory;
cache memory;
logic coupled to the cache memory to request data andor one or more instructions and to issue a request hint prior to or while identifying whether the requested data andor instruction(s) are in the cache memory, the logic to issue a memory fetch request if the requested data andor instruction(s) are not in the cache memory; and
a memory controller coupled to the logic and to the main memory and comprising a buffer, the memory controller to receive the request hint and to access the main memory to fetch data andor one or more instructions in response to the request hint and store the accessed data andor instruction(s) in the buffer, the memory controller to return to the logic the accessed data andor instruction(s) from the buffer in response to the memory fetch request.
15. The system of claim 14, wherein the cache memory comprises a primary cache memory.
16. The system of claim 14, wherein the cache memory comprises a secondary cache memory.
17. The system of claim 14, wherein the cache memory comprises primary and secondary cache memory, the logic to identify whether the requested data andor instruction(s) are in the primary cache memory and to issue the request hint if the requested data andor instruction(s) are not in the primary cache memory.
18. The system of claim 14, wherein the memory controller comprises a write buffer to store data andor instruction(s) to be written to the main memory, the memory controller to identify whether the requested data andor instruction(s) are stored in the write buffer in response to the request hint.
19. The system of claim 14, wherein the memory controller comprises a write buffer to store data andor instruction(s) to be written to the main memory, the memory controller to identify whether the requested data and instruction(s) are stored in the write buffer in response to the memory fetch request.
20. The system of claim 14, wherein the logic comprises instruction processing logic to issue the request hint.
21. The system of claim 14, wherein the logic comprises primary cache control logic to issue the request hint.
22. The system of claim 14, wherein the cache memory, the logic, and the memory controller are integrated.