1. A folding apparatus for folding a web of a maximum web width or that is divided into two partial web streams of equal width comprising:
a main former for receiving webs up to the maximum web width; and
a smaller former for receiving webs of up to approximately one-half of the maximum web width
wherein the main former includes a main former nose and the smaller former includes a smaller former nose and the main and smaller formers are arranged such that the main former nose and the smaller former nose lie substantially in a common perpendicular plane when viewed from a side of the folding apparatus such that a partial web stream emerging from the main former and a partial web stream emerging from the smaller former can undergo further processing almost congruently after folding.
2. A folding apparatus according to claim 1, wherein the smaller former is laterally displaceable.
3. A folding apparatus according to claim 1, wherein the partial web streams emerging from the main former and the smaller former can be fed to a folding or cutting device.
4. A folding apparatus according to claim 1, wherein the partial web streams emerging from the main former and the smaller former can be fed to separate apparatuses for further processing.
5. A folding apparatus according to claim 1, wherein the smaller former is arranged within lateral boundaries defined by the maximum web width receivable by the main former.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multi-plane flash memory array comprising:
a first plane of flash memory cells in which bad columns are replaced with replacement columns and are not used for storage of data; and
a second plane of flash memory cells in which bad columns are used for storage of data, replacement columns of the second plane used to store Error Correction Code (ECC) encoded data.
2. The multi-plane flash memory array of claim 1 wherein the first plane has a first number of bad columns and the second plane has a second number of bad columns, the first number being less than the second number.
3. The multi-plane flash memory array of claim 2 wherein the first plane is on a first die and the second plane is on a second die.
4. The multi-plane flash memory array of claim 3 wherein the first die and the second die are selected for the multi-plane flash memory array based on the first number and the second number.
5. The multi-plane flash memory array of claim 4 further comprising a plurality of additional dies, each of the plurality of additional dies chosen based on respective numbers of bad columns in the dies.
6. A nonvolatile memory system comprising:
at least one bad column located in a memory array; and
a soft-input ECC decoder adapted to receive compressed location information as first soft data indicating low likelihood for hard data obtained from the at least one bad column, and further configured to decode the hard data obtained from the at least one bad column in combination with the soft data indicating low likelihood for the hard data obtained from the at least one bad column.
7. The nonvolatile memory system of claim 6 wherein the soft-input ECC decoder is further adapted to apply a low likelihood for hard data obtained from any column which shares the compressed location information of the at least one bad column.
8. The nonvolatile memory system of claim 6 wherein the soft-input ECC decoder is further adapted to receive high resolution read data from the at least one bad column combined with the first soft data.
9. The nonvolatile memory system of claim 6 wherein the memory array consists of a plurality of columns, each of the plurality of columns containing a plurality of bit lines, and wherein an individual bad column contains at least one defective bit line.
10. The nonvolatile memory system of claim 6 further comprising at least one defective bit line in the at least one bad column, and wherein the compressed location information includes compressed bit line location information.
11. A memory array comprising:
a plurality of bad columns in the memory array, the plurality of bad columns ranked according to a number of bad bit lines per column;
redundant columns that replace high-ranked bad columns;
a record that records low-ranked bad column, low-ranked bad columns storing data;
identifying data from the low-ranked bad columns from the record; and
a soft-input Error Correction Code (ECC) decoder in communication with the record, the soft-input ECC decoder adapted to identify data from the low-ranked bad columns from the record and to apply a low likelihood to the data from the low-ranked bad columns.
12. The memory array of claim 11 further comprising one or more redundant columns that are not used for replacement of high-ranked bad columns and that are adapted to provide additional redundancy for stored data.
13. The memory array of claim 11 wherein high-ranked bad columns have a number of bad bit lines that is greater than a predetermined number and low-ranked bad columns have a number of bad bit lines that is less than or equal to the predetermined number.
14. The memory array of claim 11 wherein the identified bad columns are ranked according to ECC results from data stored in the bad columns.
15. The method of claim 11 wherein the memory array is a NAND flash memory array.