1. A method for optimising transistor performance in an integrated circuit, comprising:
providing an integrated circuit having at least two cells, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active regions each cell having a connection between an active diffusion region and a power rail;
identifying at least two adjacent cells each having a corresponding connection between an active region to the same power rail; and
joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells.
2. The method of claim 1 wherein the active regions comprise a positive diffusion area, a negative diffusion area and a gate area.
3. The method of claim 2 wherein the connected diffusion is the negative diffusion area.
4. The method of claim 2 wherein the connected diffusion is the positive diffusion area.
5. The method of claim 2 wherein each negative diffusion area of each adjacent cell are connected and each positive diffusion area of each adjacent cell are connected.
6. The method of claim 1 wherein the corresponding connection is positioned along the edge of the cell forming a boundary between the two cells and the two corresponding connections.
7. The method of claim 1 further comprising reorientating a cell having a corresponding connection positioned along an edge, the cell being reoriented with the edge having the corresponding connection adjacent to and forming the boundary between the two cells for joining the diffusion areas.
8. The method of claim 1 wherein the non-active area is shallow trench isolation (STI) region.
9. The method of claim 1 wherein the active areas and non-active areas are comprised of materials having different physical properties.
10. The method of claim 1 wherein the joining step comprises applying a growshrink procedure to join the diffusion areas of each cell.
11. The method of claim 1 wherein the integrated circuit is an application specific integrated circuits (ASIC) having the cells arranged using synthesis and place and route tools into rows interconnected to effect the ASIC’s function.
12. The method of claim 1 wherein the cells are standard cells.
13. The method of claim 1 wherein the integrated circuit is an application specific integrated circuits (ASIC) having cells arranged and interconnected using custom placement tools to effect the ASIC’s function.
14. The method of claim 1 wherein the cells are custom transistor-level layout cells.
15. A method for building an integrated circuit having a connected diffusion cell architecture, comprising:
providing a logic cell library having at least one cell, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail;
placing cells from the logic cell library into the integrated circuit;
identifying at least two adjacent cells in the integrated circuit each having a corresponding connection between an active region to the same power rail; and
joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells.
16. The method of claim 15 wherein the active regions comprise a positive diffusion area, a negative diffusion area and a gate area.
17. The method of claim 16 wherein the connected diffusion is the negative diffusion area.
18. The method of claim 16 wherein the connected diffusion is the positive diffusion area.
19. The method of claim 16 wherein each negative diffusion area of each adjacent cell are connected and each positive diffusion area of each adjacent cell are connected.
20. The method of claim 15 wherein the corresponding connection is positioned along the edge of the cell forming a boundary between the two cells and the two corresponding connections.
21. The method of claim 15 further comprising reorientating a cell having a corresponding connection positioned along an edge, the cell being reoriented with the edge having the corresponding connection adjacent to and forming the boundary between the two cells for joining the diffusion areas.
22. The method of claim 15 wherein the non-active area is shallow trench isolation (STI) region.
23. The method of claim 15 wherein the active areas and non-active areas are comprised of materials having different physical properties.
24. The method of claim 15 wherein the joining step comprises applying a growshrink procedure to join the diffusion areas of each cell.
25. The method of claim 15 wherein the integrated circuit is an application specific integrated circuits (ASIC) having the cells arranged using synthesis and place and route tools into rows interconnected to effect the ASIC’s function.
26. The method of claim 15 wherein the cells are standard cells.
27. The method of claim 15 wherein the integrated circuit is an application specific integrated circuits (ASIC) having cells arranged and interconnected using custom placement tools to effect the ASIC’s function.
28. The method of claim 15 wherein the cells are custom transistor-level layout cells.
29. The method of claim 15 wherein the joining step comprises applying an abutment algorithm to join the diffusion areas of each cell.
30. An integrated circuit having a connected diffusion cell architecture, comprising:
at least two adjacent cells, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail;
additional diffusion area across the boundary between the cells joining the respective active diffusion region associated with the corresponding connection of each cell forming the connected diffusion of the two adjacent cells.
31. The integrated circuit of claim 30 wherein the active regions comprise a positive diffusion area, a negative diffusion area and a gate area.
32. The integrated circuit of claim 31 wherein the connected diffusion is the negative diffusion area.
33. The integrated circuit of claim 31 wherein the connected diffusion is the positive diffusion area.
34. The integrated circuit of claim 31 wherein each negative diffusion area of each adjacent cell are connected and each positive diffusion area of each adjacent cell are connected.
35. The integrated circuit of claim 30 wherein the non-active area is shallow trench isolation (STI) region.
36. The integrated circuit of claim 30 wherein the active areas and non-active areas are comprised of materials having different physical properties.
37. The integrated circuit of any one of claim 30 wherein the cells are standard cells.
38. The integrated circuit of any one of claim 30 wherein the cells are custom transistor-level layout cells.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An adjustable hinge for a cushion and a seat body on a sofa, the adjustable hinge comprising:
an insertion tube adapted to attached to the cushion and having a distal end and multiple notches defined in the distal end; and
a tube holder with a hole adapted to embed inside the seat body, rotatably receiving the insertion tube and having a bar formed inside the hole to correspondingly engage paired two of the multiple notches for positioning.
2. The adjustable hinge as claimed in claim 1, wherein the insertion tube has multiple ribs longitudinally formed on an outer periphery of the insertion tube;
the tube holder has multiple grooves longitudinally defined on an inner periphery of the tube holder.