1. A system for performing video decode and deblock on a video frame, the video frame comprise a plurality of macroblocks, the system comprises:
a decoder, configured to decode the plurality of macroblocks;
a deblock buffer, comprising a plurality of counters, each of the plurality of counters corresponds to a macroblock group of the plurality of macroblocks respectively, the macroblock group of the macroblocks comprises a predetermined amount of neighboring macroblocks, and the counter is incremented by one in response to one of the macroblocks of the corresponding macroblock group is decoded; and
a deblock filter, configured to deblock the corresponding macroblock group in response to the counter is incremented to a fixed value.
2. The system of claim 1, wherein the macroblock group comprises N\xd7M neighboring macroblocks of the video frame.
3. The system of claim 2, wherein each of the plurality of counters comprises k bits, and k satisfies 2k\u2267(N\xd7M)+1.
4. The system of claim 2, where in the fixed value is N\xd7M.
5. The system of claim 2, wherein N\xd7M is at least 2.
6. The system of claim 1, wherein the deblock filter deblocks the macroblock groups in a predetermined order.
7. The system of claim 6, wherein the deblock filter deblocks the macroblock group in response to the corresponding counter of the macroblock group is incremented to the fixed value and macroblock groups at left and at top of the macroblock group are decoded.
8. The system of claim 6, wherein the predetermined order is from left to right and from top to bottom.
9. The system of claim 1, wherein the video frame comprises A\xd7B pixels, A and B are positive integers.
10. The system of claim 9, wherein the video frame comprises C\xd7D macroblocks, and each of the macroblocks comprises E\xd7F pixels, C, D, E, and F are positive integers and A\xd7B=C\xd7D\xd7E\xd7F.
11. The system of claim 1, wherein the decoder decodes in H.264AVC.
12. A method for decoding and deblocking a video frame, the video frame comprises a plurality of macroblocks; the method comprising:
decoding the plurality of macroblocks;
incrementing one of a plurality counters by one in response to one of a plurality of macroblocks is decoded, the plurality of macroblock is partitioned into a plurality of macroblock groups and each of the macroblock group corresponds to a counter; and
deblocking one of the macroblock groups in response to the counter corresponding to the macroblock group is incremented to a fixed value.
13. The method of claim 12, wherein each of the macroblock group comprises N\xd7M neighboring macroblocks.
14. The method of claim 13, wherein each of the plurality of counters comprises k bits, and k satisfies 2k\u2267(N\xd7M)+1.
15. The method of claim 13, wherein the fixed value is N\xd7M.
16. The method of claim 13, wherein N\xd7M is at least 2.
17. The method of claim 12, wherein the deblocking is performed in a predetermined order.
18. The system of claim 17, further comprising deblocking the macroblock group in response to the counter corresponding to the macroblock group is incremented to the fixed value and macroblock groups having prior order than the macroblock group are decoded.
19. The system of claim 17, wherein the predetermined order is from left to right, from top to bottom.
20. The system of claim 12, wherein the video frame comprises A\xd7B pixels, A and B are positive integers.
21. The system of claim 20, wherein the video frame comprises C\xd7D macroblocks, and each of the macroblocks comprises E\xd7F pixels, C, D, E, and F are positive integers and A\xd7B=C\xd7D\xd7E\xd7F.
22. The system of claim 12, wherein the decoding is performed in H.264AVC standard.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor test apparatus for testing a semiconductor device, comprising:
a capture board having an input terminal to which a measurement signal output from a device under measurement is input, and an amplifier circuit which amplifies the measurement signal input to the input terminal;
a cable which sends the measurement signal from the device under measurement to the capture board;
a buffer connected between the cable and the device under measurement to drive the cable;
a performance board on which the buffer is mounted;
a reference signal generator which applies a reference signal for calibration of the buffer across the device under measurement and the buffer; and
a switch which switches between the measurement signal from the device under measurement and the reference signal from the reference signal generator so that one of them is input to the buffer.
2. The semiconductor test apparatus according to claim 1, wherein the reference signal generator is a gain correcting reference signal generator which outputs a reference signal indicating a predetermined voltage value and then applies the reference signal to the buffer.
3. The semiconductor test apparatus according to claim 1, wherein the reference signal generator is a voltage offset correcting reference signal generator which outputs a reference signal indicating a voltage value of 0 V and then applies the reference signal to the buffer.
4. The semiconductor test apparatus according to claim 1, wherein the reference signal generator is a timing offset correcting reference signal generator which outputs a signal having a phase of 0 and applies the reference signal to the buffer.
5. The semiconductor test apparatus according to claim 1, wherein the device under measurement is a charge coupled device or a complementary metal-oxide semiconductor constituting an image sensor.